CS8416-CSZR Просмотр технического описания (PDF) - Cirrus Logic
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CS8416-CSZR Datasheet PDF : 60 Pages
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CS8416
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE
(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF)
Parameter
Symbol
Min
Max
CCLK Clock Frequency
(Note 12)
fsck
0
6.0
CS High Time Between Transmissions
tcsh
1.0
-
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
CCLK Falling to CDOUT Stable
Rise Time of CDOUT
Fall Time of CDOUT
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
tcss
20
-
tscl
66
-
tsch
66
-
tdsu
40
-
(Note 13)
tdh
15
-
tpd
-
50
tr1
-
25
tf1
-
25
(Note 14)
tr2
-
100
(Note 14)
tr2
-
100
Unit
MHz
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
12. If Fs is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fs. This is dic-
tated by the timing requirements necessary to access the Channel Status memory. Access to the con-
trol register file can be carried out at the full 6 MHz rate. The minimum allowable input sample rate is
32 kHz, so choosing CCLK to be less than or equal to 4.1 MHz should be safe for all possible conditions.
13. Data must be held for sufficient time to bridge the transition time of CCLK.
14. For fsck <1 MHz.
CS
t css
CCLK
t r2
CDIN
CDOUT
t scl t sch
t f2
t dsu
t dh
t pd
Figure 3. SPI Mode Timing
t csh
10
DS578F3
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