CDB8416 Просмотр технического описания (PDF) - Cirrus Logic
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CDB8416 Datasheet PDF : 42 Pages
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CS8406
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS
(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF)
Parameter
Symbol Min Typ
SDIN Setup Time Before ISCLK Active Edge
SDIN Hold Time After ISCLK Active Edge
Master Mode
(Note 5)
tds
(Note 5)
tdh
10
-
8
-
OMCK to ISCLK active edge delay
OMCK to ILRCK delay
ISCLK and ILRCK Duty Cycle
Slave Mode
(Note 5)
tsmd
(Note 6)
tlmd
0
-
0
-
-
50
ISCLK Period
ISCLK Input Low Width
ISCLK Input High Width
ISCLK Active Edge to ILRCK Edge
ILRCK Edge Setup Before ISCLK Active Edge
tsckw
36
-
tsckl
14.4
-
tsckh
14.4
-
(Note 7)
tlrckd
10
-
(Note 8)
tlrcks
10
-
Max
-
-
17
16
-
-
-
-
-
-
Units
ns
ns
ns
ns
%
ns
ns
ns
ns
ns
Notes:
5. The active edge of ISCLK is programmable in Software Mode.
6. The polarity of ILRCK is programmable in Software Mode.
7. Prevents the previous ISCLK edge from being interpreted as the first one after ILRCK has changed.
8. This setup time ensures that this ISCLK edge is interpreted as the first one after ILRCK has changed.
ISCLK
(output)
ILRCK
(output)
t smd
t lmd
OMCK
(input)
Figure 1. Audio Port Master Mode Timing
ILRCK
(input)
ISCLK
(input)
t lrckd
t lrcks
t sckh
tsckl
t sckw
SDIN
tds
tdh
Figure 2. Audio Port Slave Mode and Data Input Timing
6
DS580F5
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