CS7620-IQ Просмотр технического описания (PDF) - Cirrus Logic

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производитель

CS7620-IQ

CCD Imager Analog Processor

Cirrus Logic 

CS7620

Ideal

CCD Signal

internal

sampling

clocks

CK_FT

CK_DT

Figure 19. Detailed Signal Timing Showing Internal Clock Phases

Ideal

CCD Signal

H1

H2

default

settings

H3

H4

RG

t4 t5 t6 t7 t0 t1 t2 t3 t4 t5 t6 t7 t0 t1 t2 t3

Figure 20. Default Timing of Horizontal Signals to the CCD

trolled through the serial interface as described be-

low.

The pixel period is broken down into 8 equal time

periods. By delaying the clock a given number of

these time periods, different phases are created.

This is shown in Figure 19. These clock phases are

labeled t0-t7 and are shown relative to an idealized

CCD signal and the internal sampling signals.

Using these eight clock phases, the user may set the

rising and falling edges of each horizontal pixel

clock at 1/8 of a pixel clock period. In addition, the

user may set each horizontal signal to a default

state when the output lines are to be held constant

during blanking. The default timing for the hori-

zontal signals is shown in Figure 20 and Table 2.

See the register listing for more details.

Signal

H1

H2

H3

H4

Rising edge

t0

t2

t4

t6

Falling edge

t5

t7

t1

t3

Hold level

high (‘1’)

high (‘1’)

high (‘1’)

low (‘0’)

Table 2. Default Phases for Horizontal Signal Edges

18

DS301PP2

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