CS5529-AP(1997) Просмотр технического описания (PDF) - Cirrus Logic

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CS5529-AP
(Rev.:1997)

16-Bit, Programmable ∆Σ ADC with 6-Bit Latch

Cirrus Logic 

CS5529

FAQs

FAQs

1) Do you have a four channel part?

A: Not at this time, but we have plans to do a multi-channel product Q4 ‘97.

We also have 4 digital output lines which can be used to control either

switches or a multiplexer through the ADC’s serial port, thus eliminating

the use of an extra port on the system µC and additional opto-isolators in

isolated applications.

2) How does the 4-bit digital latch on a DS ADC allow me to change chan-

nels?

A: The CS5525 and CS5526 as well as the CS5504 family of ADC’s are

designed to settle in one conversion cycle. This means a mux can be

switched from channel-to-channel with every conversion while maintain-

ing resolution and accuracy.

3) What determines the input span of the converter?

A: Performing a full scale gain calibration, or modifying the reference volt-

age. For example, if the reference voltage is reduced by 50% the default

input ranges scale by one half. Example:

Vref = 2.5 V, Vin = 25 mV to 5 V and

Vref = 1.25 V, Vin = 12.5 mV to 2.5 V.

4) How does the output word rate affect the ADC’s bandwidth?

A: The input bandwidth is limited to 1/2 the selected output word rate due to

the Nyquist theory of sampling. Example: With the default 15 Hz output

word rate the available signal bandwidth of the ADC is 7.5 Hz.

5) What is recommended if I need more or less bandwidth than is provided

by the on-chip digital filter?

A: Use an external clock between 30 kHz and 100 kHz to scale the digital

filters corner frequency accordingly. Example: Using a 3x clock =

3x32.768 kHz = 3 x the word rate = 3 x 3.76 Hz to 3 x 202 Hz = 11.28 Hz

to 606 Hz.

PI246PP1 OCT ‘97

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