CS5464 Просмотр технического описания (PDF) - Cirrus Logic
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CS5464 Datasheet PDF : 46 Pages
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CS5464
Parameter
Symbol Min
Typ
Low-level Input Voltage (VD = 3.3 V)
All Pins Except XIN and SCLK and RESET
XIN VIL
-
-
-
-
SCLK and RESET
-
-
High-level Output Voltage
Iout = +5 mA VOH (VD+) - 1.0
-
Low-level Output Voltage
Iout = -5 mA (VD = +5V) VOL
-
-
Iout = -2.5 mA (VD = +3.3V)
-
-
Input Leakage Current
(Note 16) Iin
-
±1
3-state Leakage Current
IOZ
-
-
Digital Output Pin Capacitance
Cout
-
5
Max Unit
0.48
V
0.3
V
0.2 VD+ V
-
V
0.4
V
0.4
V
±10
µA
±10
µA
-
pF
Notes: 10. All measurements performed under static conditions.
11. If a crystal is used, XIN frequency must remain between 2.5 MHz - 5.0 MHz. If an external oscillator is
used, XIN frequency range is 2.5 MHz - 20 MHz, but K must be set so that MCLK is between
2.5 MHz - 5.0 MHz.
12. If external MCLK is used, the duty cycle must be between 45% and 55% to maintain this specification.
13. The frequency of CPUCLK is equal to MCLK.
14. The minimum FSCR is limited by the maximum allowed gain register value. The maximum FSCR is
limited by the full-scale signal applied to the channel input.
15. Configuration Register bits PC[6:0] are set to “0000000”.
16. The MODE pin is pulled low by an internal resistor.
10
DS682PP1
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