CS5463 Просмотр технического описания (PDF) - Cirrus Logic
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CS5463 Datasheet PDF : 46 Pages
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CS5463
ANALOG CHARACTERISTICS (Continued)
Parameter
Symbol Min
Analog Inputs (Voltage Channel)
Differential Input Range
[(VIN+) - (VIN-)] VIN
-
Total Harmonic Distortion
THD
65
Crosstalk with Current Channel at Full Scale (50, 60 Hz)
-
Input Capacitance
All Gain Ranges IC
-
Effective Input Impedance
EII
2
Noise (Referred to Input)
Offset Drift (Without the High Pass Filter)
NV
-
OD
-
Gain Error
(Note 3) GE
-
Temperature Channel
Temperature Accuracy
T
-
Power Supplies
Power Supply Currents (Active State)
IA+ PSCA
-
ID+ (VA+ = VD+ = 5 V) PSCD
-
ID+ (VA+ = 5 V, VD+ = 3.3 V) PSCD
-
Power Consumption Active State (VA+ = VD+ = 5 V) PC
-
(Note 4)
Active State (VA+ = 5 V, VD+ = 3.3 V)
-
Stand-by State
-
Sleep State
-
Power Supply Rejection Ratio
(Note 5)
(50, 60 Hz)
Voltage Channel PSRR
45
Current Channel
70
PFMON Low-voltage Trigger Threshold
(Note 6) PMLO
2.3
PFMON High-voltage Power-on Trip Point
(Note 7) PMHI
-
Typ
500
75
-70
0.2
-
140
16.0
±3.0
±5
1.1
2.9
1.7
21
11.6
8
10
-
65
75
2.45
2.55
Max Unit
-
mVP-P
-
dB
-
dB
-
pF
-
MΩ
-
µVrms
-
µV/°C
%
-
°C
-
mA
-
mA
-
mA
29
mW
17.5 mW
-
mW
-
µW
-
-
dB
-
dB
-
V
2.7
V
Notes: 3. Applies before system calibration.
4. All outputs unloaded. All inputs CMOS level.
5. Measurement method for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV
(zero-to-peak) (60 Hz) sinewave is imposed onto the +5 V DC supply voltage at VA+ and VD+ pins. The
“+” and “-” input pins of both input channels are shorted to AGND. Then the CS5463 is commanded to
continuous conversion acquisition mode, and digital output data is collected for the channel under test.
The (zero-to-peak) value of the digital sinusoidal output signal is determined, and this value is converted
into the (zero-to-peak) value of the sinusoidal voltage (measured in mV) that would need to be applied
at the channel’s inputs, in order to cause the same digital sinusoidal output. This voltage is then defined
as Veq. PSRR is then (in dB):
PSRR
=
20 ⋅ log
-1---5---0--
Veq
6. When voltage level on PFMON is sagging, and LSD bit = 0, the voltage at which LSD is set to 1.
7. If the LSD bit has been set to 1 (because PFMON voltage fell below PMLO), this is the voltage level on
PFMON at which the LSD bit can be permanently reset back to 0.
8
DS678F2
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