SCLK output
LRCK output
SDATA
t mslr
t sdo
SCLK output
LRCK output
SDATA
CS5330A/31A
t mslr
t sdo
SCLK to SDATA LRCK - MASTER mode (CS5330A)
tslr1 tslr2
tsclkl tsclkh
SCLK input
(SLAVE mode)
LRCK input
(SLAVE mode)
t lrdss
t sclkw
t dss
SDATA
MSB
MSB-1 MSB-2
SCLK to SDATA LRCK - MASTER mode (CS5331A)
tslr1 tslr2
tsclkl tsclkh
SCLK input
(SLAVE mode)
LRCK input
(SLAVE mode)
t sclkw
t dss
SDATA
MSB
MSB-1
SCLK to LRCK & SDATA - SLAVE mode (CS5330A) SCLK to LRCK & SDATA - SLAVE mode (CS5331A)
+5V
Analog
10 µF + 0.1 µF
150 Ω .47 µF
Analog
Input
Circuits
**
150 Ω .47 µF
**
8
AINL
.01 µF
5
AINR
.01 µF
7
VA+
CS5330A
CS5331A
MCLK 4
SCLK 2
LRCK 3
SDATA 1
1 kΩ
1 kΩ
1 kΩ
1 kΩ
Audio Data
Processor
Timing
Logic
&
Clock
* Required for Master mode only
** Optional if analog input circuits biased
to within ± 5% of CS5330A/CS5331A
nominal input bias voltage
AGND
6
* 47 kΩ
Figure 1. Typical Connection Diagram
8
DS138F5