CDB5381 Просмотр технического описания (PDF) - Cirrus Logic
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CDB5381 Datasheet PDF : 24 Pages
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3. APPLICATIONS
CS5381
3.1 Operational Mode/Sample Rate Range Select
The output sample rate, Fs, can be adjusted from 2 kHz to 216 kHz. The CS5381 must be set to the proper
speed mode via the mode pins, M1 and M0. Refer to Table 1.
M1 (Pin 14)
0
0
1
1
M0 (Pin 13)
0
1
0
1
MODE
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
Reserved
Table 1. CS5381 Mode Control
Output Sample Rate (Fs)
2 kHz - 54 kHz
50 kHz - 108 kHz
100 kHz - 216 kHz
3.2 System Clocking
The device supports operation in either Master Mode, where the left/right and serial clocks are synchronous-
ly generated on-chip, or Slave Mode, which requires external generation of the left/right and serial clocks.
The device also includes a master clock divider in Master Mode where the master clock will be internally
divided prior to any other internal circuitry when MDIV is enabled, set to logic 1. In Slave Mode, the MDIV
pin needs to be disabled, set to logic 0.
3.2.1
Master Mode
In Master mode, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally derived
from the master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as shown
in Figure 23. Refer to Table 2 for common master clock frequencies.
÷ 256
Single
Speed
00
MCLK
÷1
0
÷2
1
÷ 128
Double
Speed
01
÷ 64
Quad
Speed
10
LRCK Output
(Equal to Fs)
M1 M0
MDIV
÷4
Single
Speed
00
÷2
Double
Speed
01
÷1
Quad
Speed
10
SCLK Output
Figure 23. CS5381 Master Mode Clocking
DS563F2
15
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