CS5378(2005) Просмотр технического описания (PDF) - Cirrus Logic

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CS5378
(Rev.:2005)

Low-power Single-channel Decimation Filter

Cirrus Logic 

CS5378

SPI Registers

Name

SPICTRL

SPICMD

SPIDAT1

SPIDAT2

Addr.

00 - 02

03 - 05

06 - 08

09 - 0B

Type

R/W

R/W

R/W

R/W

# Bits

8, 8, 8

8, 8, 8

8, 8, 8

8, 8, 8

SPI Control

SPI Command

SPI Data 1

SPI Data 2

Digital Filter Registers

Description

Name

CONFIG

RESERVED

GPCFG

RESERVED

FILTCFG

GAIN

RESERVED

OFFSET

RESERVED

TIMEBRK

TBSCFG

TBSGAIN

SYSTEM1

SYSTEM2

VERSION

SELFTEST

Addr.

00

01-0D

0E

0F-1F

20

21

22-24

25

26-28

29

2A

2B

2C

2D

2E

2F

Type

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

# Bits

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

Description

Hardware Configuration

Reserved

GPIO[7:0] Direction, Pull-up Enable, and Data

Reserved

Digital Filter Configuration

Gain Correction

Reserved

Offset Correction

Reserved

Time Break Delay

Test Bit Stream Configuration

Test Bit Stream Gain

User Defined System Register 1

User Defined System Register 2

Hardware Version ID

Self-Test Result Code

Table 3. SPI and Digital Filter Registers

PLL[2:0]

111

110

101

100

011

010

001

000

Mode Selection on Reset

32.768 MHz clock input (PLL bypass).

1.024 MHz clock input.

2.048 MHz clock input.

4.096 MHz clock input.

32.768 MHz clock input (PLL bypass).

1.024 MHz manchester input.

2.048 MHz manchester input.

4.096 MHz manchester input.

BOOT

1

0

Mode Selection on Reset

EEPROM boot

Microcontroller boot

Configuration Note:

States of the PLL[2:0] and BOOT pins are

latched immediately after reset to select modes.

These pins have a weak (~100 kΩ) pull-up re-

sistor enabled by default. An external 10 kΩ

pull-down is required to set a low condition.

Table 4. PLL and BOOT Mode Reset Configurations

DS639F1

11

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