CS5372-BS Просмотр технического описания (PDF) - Cirrus Logic
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CS5372-BS Datasheet PDF : 22 Pages
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CS5371/CS5372
ANALOG CHARACTERISTICS (Continued)
Parameter
Symbol Min
Specified Temperature Range
Input Characteristics
TA
-40
Input Signal Frequencies
(Note 8) BW
DC
Input Voltage Range
(Note 9) VIN
-
Input Over-range Voltage Tolerance
Input Signal plus Common Mode
(Note 9) IOVR
5
VA-
Common Mode Rejection Ratio
CMRR
-
Channel Crosstalk, CS5372 only
CXT
-
Voltage Reference Input
VREF
(VREF+) - (VREF-)
-
VREF Current
-
Power Supplies
DC Power Supply Currents
LPWR = 0; MCLK = 2.048 MHz
LPWR = 1; MCLK = 1.024 MHz
(Note 10 and 11)
Analog VA
-
Digital VD
-
Analog VA
-
Digital VD
-
Power Down
CS5371
CS5372
PD
PWDN = 1
-
PWDN = 1, MCLK = 0
-
PWDN1 or PWDN2 = 1
-
PWDN1 = PWDN2 = 1
-
PWDN1 = PWDN2 = 1; MCLK = 0
-
Power Supply Rejection DC - 128 kHz
(Note 12) PSRR
-
Typ
-
-
-
-
-
90
-120
2.5
-
Max Unit
+85
°C
1644
5
-
VA+
-
-
Hz
Vp-p
%F.S.
V
dB
dB
-
V
120
µA
5.0
7.0
mA
0.1
0.2
mA
3.0
4.5
mA
0.1
0.2
mA
1
-
mW
10
-
µW
25
-
mW
1
-
mW
10
-
µW
90
-
dB
Notes: 8. The upper bandwidth limit is determined by the CS5376 digital filter. A simple single pole anti-alias filter
with a -3 dB frequency at (MCLK / 256) should be placed in front of each channel.
9. The input voltage range is for the configuration depicted in Figure 3, the System Connection Diagram,
and applies to signal frequencies from DC to the stop-band frequency selected in the CS5376.
10. Per channel. All outputs unloaded. All digital inputs forced to VD or GND respectively.
11. In Low Power Mode LPWR = 1, the Master Clock MCLK is reduced to 1.024 MHz. This reduces the
signal bandwidth by a factor of 2.
12. Tested with a 100 mVp-p sine wave applied separately to each supply.
4
DS255PP2
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