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CS485XX

32-bit Audio Decoder DSP Family

Cirrus Logic 

CS485xx Family Data Sheet

32-bit Audio Decoder DSP Family

4.1.2 DMA Controller

The powerful 8-channel DMA controller can move data between 8 on-chip resources. Each resource

has its own arbiter: X, Y, and P RAMs/ROMs and the peripheral bus. Modulo and linear addressing

modes are supported, with flexible start address and increment controls. The service intervals for

each DMA channel, as well as up to 6 interrupt events, are programmable.

4.2 On-chip DSP Peripherals

4.2.1 Digital Audio Input Port (DAI)

Each version of the CS485xx supports a different number of input channels. Refer to Table 2 on

page 7 for more details.

The DAI port supports a wide variety of data input formats at sample rates (Fs) as high as 192 kHz.

T The port is capable of accepting PCM or DSD formats. Up to 32-bit word lengths are supported. DSD

is supported and internally converted to PCM before processing. The DAI also supports a time

F division multiplexed (TDM) one-line data mode, that packs PCM audio on a single data line (the total

number possible depends on the ratio of SCLK to LRCLK and the version of chip. For example on

A the CS48520 only 4 ch of PCM are supported in one line mode and on the CS48560 up to 8

channels are supported.).

R The port has two independent slave-only clock domains. Each data input can be independently

assigned to a clock domain. The sample rate of the input clock domains can be determined

D automatically by the DSP, off-loading the task of monitoring the SPDIF receiver from the host. A time-

stamping feature allows the input data to be sample-rate converted via software.

L 4.2.2 Digital Audio Output Port (DAO)

I Each version of the CS485xx supports a different number of output channels. Refer to Table 2 on

IA H page 7 for more details.

DAO port supports PCM resolutions of up to 32-bits. The port supports sample rates (Fs) as high as

T P 192 kHz. The port can be configured as an independent clock domain mastered by the DSP, or as a

clock slave if an external MCLK or SCLK/LRCLK source is available. One of the serial audio pins can

N L be re-configured as a SPDIF transmitter that drives a bi-phase encoded S/PDIF signal (data with

embedded clock on a single line).

E E The DAO also supports a time division multiplexed (TDM) one-line data mode, that packs multiple

ID D channels of PCM audio on a single data line.

4.2.3 Serial Control Port (I2C® or SPI™)

F The on-chip serial control port is capable of operating as master or slave in either SPI™ or I2C®

modes. Master/Slave operation is chosen by mode select pins when the CS485xx comes out of

N Reset. The serial clock pin can support frequencies as high as 25 MHz in SPI mode (SPI clock speed

must always be ≤ (Fdclk/2)). The CS485xx serial control port also includes a pin for flow control of the

communications interface (SCP_BSY) and a pin to indicate when the DSP has a message for the

O host (SCP_IRQ).

C 4.2.4 GPIO

Many of the CS485xx peripheral pins are multiplexed with GPIO. Each GPIO can be configured as

an output, an input, or an input with interrupt. Each input-pin interrupt can be configured as rising

edge, falling edge, active-low, or active-high.

8

©Copyright 2008 Cirrus Logic, Inc.

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