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CS4922-CL

MPEG/G.729A Audio Decoder System

Cirrus Logic 

CS4922

SWITCHING CHARACTERISTICS - BOOT INITIALIZATION (TA = 25 °C; VA+, VD+ =

5V; Inputs: Logic 0 = DGND, Logic 1 = VD+, CL = 20pF)

Parameter

Symbol

Min

Max

Units

BOOT Setup Time to RESET Rising

tbsu

350

-

ns

RESET Rising to Boot Hold Time

tbh

450

-

ns

CS Setup Time to RESET Rising

(Note 4)

tcssu

200

-

ns

RESET Rising to CS Hold Time

tcsh

400

-

ns

RESET Low Time

trlow

50

-

µs

SCK/SCL Delay Time from RESET Rising

(Note 5)

trsc

2

-

ms

SCK/SCL falling to CS rising on last byte of download

tsfcr

3

-

µs

Notes: 4. The mode of the Serial Control Port is selected by CS. CS = 1 is I2C® . CS = 0 is SPI mode.

5. This delay is necessary after any rising edge of RESET to allow time for the part to initialize and for

the on-board PLL to stabilize.

tbsu tbh

BOOT

RESET

(I2C) CS

(SPI) CS

t rlow

tcssu

tcsh

trsc

tsfcr

SCK/SCL

Figure 1. Boot Timing

7

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