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CS44L11-CZZ

Low Voltage Class-D PWM Headphone Amplifier

Cirrus Logic 

CS44L11

SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT

(GND = 0 V; all voltages with respect to 0 V.)

Parameter

Symbol

Min

SCL Clock Frequency

fscl

-

RST Rising Edge to Start

tirs

500

Bus Free Time Between Transmissions

tbuf

4.7

Start Condition Hold Time (prior to first clock pulse)

thdst

4.0

Clock Low time

tlow

4.7

Clock High Time

thigh

4.0

Setup Time for Repeated Start Condition

tsust

4.7

SDA Hold Time from SCL Falling

(Note 8)

thdd

0

SDA Setup time to SCL Rising

tsud

250

Rise Time of SCL and SDA

trc, trc

-

Fall Time SCL and SDA

tfc, tfc

-

Setup Time for Stop Condition

tsusp

4.7

Acknowledge Delay from SCL Falling

(Note 9)

tack

-

Max

100

-

-

-

-

-

-

-

-

1

300

-

(Note 10)

Unit

kHz

ns

µs

µs

µs

µs

µs

µs

ns

µs

ns

µs

ns

Notes:

8. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.

9. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.

10. 2----5---6---5-×-----F----s- for Single-Speed Mode and 1----2---8---5-×-----F----s- for Double-Speed Mode.

RST

t irs

Stop

Start

SDA

t buf

t hdst

t high

Repeated

Sta rt t rd

t hdst

Stop

t fd

t fc

t susp

SCL

t

low

t

hdd

t sud t ack

t sust

t rc

Figure 2. Control Port Timing - I²C Format

DS640PP4

9

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