CS44L11 Просмотр технического описания (PDF) - Cirrus Logic

Номер в каталоге

Компоненты Описание

Список матч

CS44L11

Low Voltage Class-D PWM Headphone Amplifier

Cirrus Logic 

CS44L11

7.1 I²C Format .................................................................................................................................... 28

7.1.1 Writing in I²C Format ........................................................................................................ 28

7.1.2 Reading in I²C Format ...................................................................................................... 28

7.2 Memory Address Pointer (MAP) ................................................................................................. 28

7.2.1 INCR (Auto Map Increment Enable) ................................................................................ 28

7.2.2 MAP3-0 (Memory Address Pointer) ................................................................................. 29

8. PARAMETER DEFINITIONS ............................................................................................................... 32

9. REFERENCES ..................................................................................................................................... 32

10. PACKAGE DIMENSIONS ................................................................................................................. 33

11. REVISION HISTORY ......................................................................................................................... 34

LIST OF FIGURES

Figure 1. Serial Audio Data Interface Timing ............................................................................................... 8

Figure 2. Control Port Timing - I²C Format................................................................................................... 9

Figure 3. Typical CS44L11 Connection Diagram Stand-Alone Mode ........................................................ 10

Figure 4. Typical CS44L11 Connection Diagram Control Port Mode......................................................... 11

Figure 5. Dynamics Control Block Diagram ............................................................................................... 20

Figure 6. De-Emphasis Curve.................................................................................................................... 22

Figure 7. Control Port Timing, I²C Format.................................................................................................. 29

Figure 8. Single-Speed Stopband Rejection .............................................................................................. 29

Figure 9. Single-Speed Transition Band .................................................................................................... 29

Figure 10. Single-Speed Transition Band (Detail)...................................................................................... 29

Figure 11. Single-Speed Passband Ripple ................................................................................................ 29

Figure 12. Double-Speed Stopband Rejection........................................................................................... 30

Figure 13. Double-Speed Transition Band................................................................................................. 30

Figure 14. Double-Speed Transition Band (Detail) .................................................................................... 30

Figure 15. Double-Speed Passband Ripple............................................................................................... 30

Figure 16. Left-Justified, up to 24-Bit Data................................................................................................. 31

Figure 17. Right-Justified, 24-Bit Data ....................................................................................................... 31

Figure 18. I²S, Up to 24-Bit Data................................................................................................................ 31

Figure 19. Right-Justified, 16-Bit Data ....................................................................................................... 31

LIST OF TABLES

Table 1. Register Quick Reference ............................................................................................................ 12

Table 2. Example Volume Settings ............................................................................................................ 14

Table 3. Example Bass Boost Settings ...................................................................................................... 15

Table 4. Example Treble Boost Settings.................................................................................................... 15

Table 5. Base Boost Corner Frequencies in Single-Speed Mode.............................................................. 16

Table 6. Base Boost Corner Frequencies in Double-Speed Mode ............................................................ 16

Table 7. Treble Boost Corner Frequencies in Single-Speed Mode............................................................ 16

Table 8. Example Limiter Attack Rate Settings.......................................................................................... 18

Table 9. Example Limiter Release Rate Settings....................................................................................... 18

Table 10. ATAPI Decode ........................................................................................................................... 19

Table 11. Single-Speed Clock Modes - Control Port Mode ....................................................................... 21

Table 12. Single-Speed Clock Modes - Stand-Alone Mode....................................................................... 21

Table 13. Double-Speed Clock Modes - Control Port Mode ...................................................................... 22

Table 14. Digital Interface Format (Stand-Alone Mode)............................................................................. 25

Table 15. Revision History ......................................................................................................................... 34

DS640PP4

3

Share Link: