CDB43L42 Просмотр технического описания (PDF) - Cirrus Logic
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CDB43L42 Datasheet PDF : 40 Pages
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CS43L42
SWITCHING CHARACTERISTICS (TA = -10 to 70° C; VL = 1.7 V - 3.6 V; Inputs: Logic 0 = GND,
Logic 1 = VL, CL = 20 pF)
Parameters
Symbol
Min
Typ Max Units
Input Sample Rate
Base Rate Mode Fs
High Rate Mode Fs
2
-
50
kHz
50
-
100
kHz
MCLK Pulse Width High
MCLK/LRCK = 1024
7
-
-
ns
MCLK Pulse Width Low
MCLK/LRCK = 1024
7
-
-
ns
MCLK Pulse Width High
MCLK/LRCK = 768
10
-
-
ns
MCLK Pulse Width Low
MCLK/LRCK = 768
10
-
-
ns
MCLK Pulse Width High
MCLK/LRCK = 512
15
-
-
ns
MCLK Pulse Width Low
MCLK/LRCK = 512
15
-
-
ns
MCLK Pulse Width High MCLK / LRCK = 384 or 192
25
-
-
ns
MCLK Pulse Width Low MCLK / LRCK = 384 or 192
25
-
-
ns
MCLK Pulse Width High MCLK / LRCK = 256 or 128
35
-
-
ns
MCLK Pulse Width Low MCLK / LRCK = 256 or 128
35
-
-
ns
External SCLK Mode
LRCK Duty Cycle (External SCLK only)
40
50
60
%
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK Period
Base Rate Mode
High Rate Mode
SCLK rising to LRCK edge delay
SCLK rising to LRCK edge setup time
SDATA valid to SCLK rising setup time
SCLK rising to SDATA hold time
Internal SCLK Mode (Note 11)
tsclkl
tsclkh
tsclkw
tsclkw
tslrd
tslrs
tsdlrs
tsdh
20
20
----------1-----------
( 128 ) F s
(---6---4--1--)---F----s-
20
20
20
20
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
-
-
ns
LRCK Duty Cycle (Internal SCLK only) (Note 12)
-
50
-
%
SCLK Period
SCLK rising to LRCK edge
SDATA valid to SCLK rising setup time
tsclkw
-------1---------
SCLK
-
-
ns
tsclkr
-
t---s---c----l-k----w---
-
µs
2
tsdlrs
(---5---1----21---)---F----s- + 10
-
-
ns
SCLK rising to SDATA hold time Base Rate Mode tsdh
(---5---1----21---)---F----s- + 15
-
-
ns
High Rate Mode tsdh
(---3---8----41---)---F----s- + 15
-
-
ns
Notes: 11. Internal SCLK Mode timing is not tested, but is guaranteed by design.
12. In Internal SCLK Mode, the LRCK duty cycle must be 50% +/− 1/2 MCLK Period.
10
DS481PP2
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