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CS4391A-KZ

24-Bit, 192 kHz Stereo DAC with Volume Control

Cirrus Logic 

CS4391A

SWITCHING CHARACTERISTICS - I2C CONTROL PORT (Inputs: logic 0 = AGND,

logic 1 = VL)

Parameter

Symbol

Min

I2C® Mode

SCL Clock Frequency

fscl

-

RST Rising Edge to Start

tirs

500

Bus Free Time Between Transmissions

tbuf

4.7

Start Condition Hold Time (prior to first clock pulse)

thdst

4.0

Clock Low time

tlow

4.7

Clock High Time

thigh

4.0

Setup Time for Repeated Start Condition

tsust

4.7

SDA Hold Time from SCL Falling

(Note 7)

thdd

0

SDA Setup time to SCL Rising

tsud

250

Rise Time of Both SDA and SCL Lines

tr

-

Fall Time of Both SDA and SCL Lines

tf

-

Setup Time for Stop Condition

tsusp

4.7

Max

100

-

-

-

-

-

-

-

-

1

300

-

Unit

KHz

ns

µs

µs

µs

µs

µs

µs

ns

µs

ns

µs

Notes: 7. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.

RST

t irs

Stop

Start

R e p e a te d

S ta rt

SDA

t buf

t hdst

t high

t hdst

tf

SCL

t

t

lo w

hdd

t sud

t sust

tr

Figure 3. I2C Control Port Timing

Stop

t susp

DS600PP3

11

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