CS4350-DZZR(2006) Просмотр технического описания (PDF) - Cirrus Logic

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CS4350-DZZR
(Rev.:2006)

192 kHz Stereo DAC with Integrated PLL

Cirrus Logic 

CS4350

Pin Name # Pin Description

VLC

5 Control Interface Power (Input) - Positive power for the hardware/software control interface

VD_FILT

6 Regulator Voltage (Output) - Filter connection for internal voltage regulator

GND

7, 19 Ground (Input) - Ground reference

RMCK

8 Recovered Master Clock (Output) - Outputs a master clock derived from LRCK

VLS

9 Serial Audio Interface Power (Input) - Positive power for the serial audio interface

SCLK

10 Serial Clock (Input) - Serial bit-clock for the serial audio interface

SDIN

LRCK

TSTO

11 Serial Audio Data Input (Input) - Input for two’s complement serial audio data

Left/Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial

12 audio data line

13 Test Output - These pins need to be floating and not connected to any trace or plane.

AOUTA+,- 14, 15, Differential Analog Outputs (Output) - The full scale differential output level is specified in “DAC Ana-

AOUTB+,- 22, 23 log Characteristics” on page 9.

AMUTEC

BMUTEC

16, 21 Mute Control (Output) - Control signals for optional mute circuit.

VBIAS

17 Positive Voltage Reference (Output) - Positive reference voltage for the internal DAC

VA

18 Analog Power (Input) - Positive power supply for the analog section

VQ

20 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage

RST

Reset (Input) - When pulled low, device will power down and reset all internal registers to their default

24 settings.

Control Port Definitions

AD1/CDOUT

1

Address Bit 1 / Serial Control Data Out (I/O) - Chip address bit 1 in I²C Mode or data output in SPI

Mode

AD0/CS

2 Address Bit 0 / Chip Select (Input) - Chip address bit 0 in I²C Mode or Chip Select in SPI Mode

SDA/CDIN

3 Serial Control Data In (I/O) - Input/Output for I²C data. Input for SPI data

SCL/CCLK

4 Serial Control Port Clock (Input) - Serial clock for the control port interface

Stand-Alone Definitions

DIF0

DIF1

DIF2

Digital Interface Format (Input) - Defines the required relationship between the Left Right Clock, Serial

1, 3, 4 Clock, and Serial Audio Data

DEM

De-emphasis (Input) - Selects the standard 15 µs/50 µs digital de-emphasis filter response for

2 44.1 kHz sample rates

Table 1. Pin Descriptions

DS691A3

7

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