CMX641AD2 Просмотр технического описания (PDF) - CML Microsystems Plc
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CMX641AD2 Datasheet PDF : 26 Pages
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Dual SPM/Security Detector/Generator
CMX641A
Package Package
D2
P4
Signal
Description
Pin No.
9
10
11
12
13
14
15
16
17
Pin No.
Name
Type
9
CH1 AMP OUT
O/P The output of the Channel 1 input amplifier.
See Figures 2 and 3.
10
CH1 AMP IN (-)
I/P
The negative input to the Channel 1 input
amplifier. See Figures 2 and 3.
11
CH1 AMP IN
I/P
The positive input to the Channel 1 Input
(+)
amplifier. See Figures 2 and 3.
12
VSS
POWER The negative supply rail (ground).
13
ENHANCED
I/P
This pin selects the device application. When
FEATURES
(logic ‘0’) the CMX641A is in Fixed Bandwidth
Operating state. When (logic ‘1’) it is in
Enhanced Features Operating state.
This pin has an internal pulldown resistor on-
chip so that when unconnected, the default state
is Fixed Bandwidth Operating state.
14
CH2 AMP IN
I/P
The positive input to the Channel 2 input
(+)
amplifier. See Figures 2 and 3.
15
CH2 AMP IN (-)
I/P
The negative input to the Channel 2 input
amplifier. See Figures 2 and 3.
16
CH2 AMP OUT
O/P The output of the Channel 2 input amplifier.
See Figures 2 and 3.
17
OP SELECT
I/P
A logic input to set the Channel 1 and Channel 2
output format. When high (logic ‘1’), the outputs
are in the Tone Follower mode; when low (logic
‘0’), the outputs are in Packet mode.
© 2002 Consumer Microcircuits Limited
5
D/641A/5
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