CMX661(2001) Просмотр технического описания (PDF) - CML Microsystems Plc
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CMX661 Datasheet PDF : 16 Pages
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Pair Gain Dual SPM Detector
CMX661
1.5 General Description
1.5.1 Description of Blocks
Crystal Oscillator and Clock Dividers
These circuits derive the internal logic clocks, decode frequencies and transmit frequencies by frequency
division of a reference frequency which is generated by the on-chip crystal oscillator. The only external
component required is a 3.579545MHz crystal, which should be connected across the XTAL and XTALN
pins. All other oscillator components are on-chip.
Input Operational Amplifiers
The input signals are applied to the CMX661 via these amplifiers, which use the external components
shown in Figure 2. The external gain setting components should be calculated by the method described
in section 1.6.4, using the values obtained from Figure 5.
SPM Tone Bandpass Filter
These are tone bandpass/audio reject filters automatically centred on the system frequency (12kHz or
16kHz) being detected. Their gain is constant so the internal device sensitivity is also constant.
Level Detection and Pulse Generator Circuits
The outputs from the bandpass filters are input to these circuits which perform the signal level
discrimination function for the CMX661. Signals which fulfil the system level requirements cause a
stream of digital pulses, one per 32 cycles of input signal, to be generated. These pulses are sent to the
period measurement circuitry.
Period Measurement Logic
This digital circuit block inputs the stream of pulses from the level detection circuits and measures their
repetition rate against a predetermined maximum and minimum. Because each pulse from the level
detect circuit occurs once per 32 cycles of input signal, this has the effect of averaging the input signal
period over this number of cycles. A valid SPM tone is recognised when 3 successive correctly spaced
pulses are received. This causes a signal to appear immediately at the relevant channel output
signifying receipt of a valid SPM signal. Depending upon the frequency, within the legal bandwidth,
received, the CMX661 should respond within 10-15ms (see section 1.7 and Figure 4).
Output Enable Circuits
These enable the output logic pins ‘Channel 1 Output’ and ‘Channel 2 Output’. These outputs can be
made high impedance by setting the OP ENABLEN pin high. When enabled, a high (logic ‘1’) indicates
the tone is absent, a low (logic ‘0’) indicates the tone is present.
1.5.2 Operating States
The CMX661 is a dual-channel SPM detector where both detectors are set to the same bandwidth and
system frequency (12kHz or 16kHz). The sensitivity of each detector is set via external components.
The decode bandwidths can be set to ±1.5%, ±3%, ±5% and ±7.5% of the nominal tone frequency by
means of the D0 and D1 logic inputs and the system frequency is set by the SYSTEM SELECT logic
input. Each decoder logic output has a very short response and deresponse time so that it forms an
‘envelope’ of the input tone. Host µC systems must decide whether the received signal fulfils the system
tone pulse length requirements. The outputs can be set to a high impedance state for device
multiplexing by use of the OP ENABLEN pin (logic '1' gives a high impedance state on the decoder
outputs, logic '0' gives a normal (logic) output on these pins).
The sensitivity of each channel is set by correct selection of external components around each channel
input amplifier. See section 1.6.4 and Figure 5 for a method of selecting amplifier gain and components
to meet a particular sensitivity requirement.
© 2001 Consumer Microcircuits Limited
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D/661/2
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