CMX635 Просмотр технического описания (PDF) - CML Microsystems Plc

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CMX635

ISDN Subscriber Processor

CML Microsystems Plc 

ISDN Subscriber Processor

CMX635

Pin Type Legend:

I

- Digital Input

O - Digital Output

I/O - Digital Bi-directional

O/D - Open Drain

Ana - Analogue Input or Output

Subscript denotes input/output levels

C - CMOS

T - TTL

Note 1: IOMRx normally TTL input but can become open drain output during bus reversal.

IOMTx normally open drain output but can become TTL input during bus reversal.

1.3.2 Pin description

STTxp, STTxn

ST bus differential transmit outputs. Upstream data in TE configuration and Downstream data in

NT configuration. The nominal amplitude is ±2.1V differential with 280Ù load which equates to

±750mV at the ST interface when the recommended line transformer is used. STTxp is positive

with respect to STTxn for transmission of the Frame Pulse bit.

Note: Particular care should be taken to avoid electro-static discharge damage to these pins as

the unpowered impedance requirements result in reduced internal protection.

STRxp, STRxn

ST bus differential receive inputs. Downstream data in TE configuration and Upstream data in NT

configuration. The nominal expected differential pulse amplitude is ±1.2V which equates to

±750mV at the ST interface with recommended components. Amplitudes down to 255mV at the

ST interface can be accommodated while signal activity above 100mV will generate a “Wake-up”

interrupt if required. Polarity need only be maintained for point to multipoint configurations.

DCL

IOM-2 interface “terminal” mode data clock operating at a nominal frequency 1.536MHz. The

DCL can be configured as an output (cmos levels) in timing master mode or as an input (ttl

levels) in timing slave mode. DCL operates at twice the IOM bit rate and is used to sample the

data on the IOM receive input.

FSC

IOM-2 interface Frame Sync operating at a nominal frequency of 8kHz. The FSC can be

configured as an output (cmos levels) in timing master mode or as an input (ttl levels) in timing

slave mode. The rising edge of FSC defines the start of an IOM frame and is nominally

synchronous with the rising edge of DCL.

IOMTx, IOMRx

IOM-2 interface transmit and receive data pins operating at a nominal bit rate of 768kbps. The

IOMTx pin equates to the IOM DD (Data Downstream) signal when the CMX635 is the upstream

device (TE configuration) and to the IOM DU (Data Upstream) signal when the CMX635 is the

downstream device (NT configuration). The IOMTx pin can be configured as open drain or active

cmos level output. The direction of the IOMTx and IOMRx pins can be reversed for certain

channels in the IOM frame.

© 2001 Consumer Microcircuits Limited

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D/635/2

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