CMX635 Просмотр технического описания (PDF) - CML Microsystems Plc

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CMX635

ISDN Subscriber Processor

CML Microsystems Plc 

ISDN Subscriber Processor

CMX635

1) Speech filter output > noise filter output

2) Speech filter output > noise filter output + programmable threshold

3) Speech filer output > noise filter output + programmable threshold +/-

hysteresis value.

• Interrupt generation when a change in any of the above conditions takes place. The

user can poll the indicator flag bits to determine the exact condition that exists within

the channel.

• A hysteresis register to prevent rapid and spurious interrupts when a slow noisy signal

moves close to the integrated background level.

1.5.8 The Processor Interface, Top Level Status and Power Control

The processor interface will automatically configure itself to operate with either multiplexed or

non-multiplexed address/data architectures and with generic Motorola or Intel control signals.

The processor interface type is configured after power-up by making a dummy write to the

CMX635, which will monitor activity on the bus control lines and decode the appropriate interface

type.

When the non-multiplexed interface is detected it is mapped as 2 addresses on the processor bus

that are distinguishable by the state of the Asel pin during the read/write cycle. The first address

(Asel set to binary 1) is the “indirect” address register for the following data access and must be

written first. The second address (Asel = binary 0) accesses the register defined by the indirect

address. Typically the single address pin (Asel) will be connected to the LSB of the processor

address bus. The indirect address is persistent and, once written, can be used for further data

accesses to the same address (i.e. block reads/writes to the Fifo data registers).

When the multiplexed interface is detected the internal register address is automatically

demultiplexed from the AD bus and thus only single read/write cycles are required.

The Top Level Status register accumulates interrupt requests from the lower level blocks (as

shown in Figure 5) and can be programmed to generate a selective device level interrupt request

dependent on the state of the top level interrupt mask. Each lower level Status Register can be

programmed to generate the interrupt requests to the top level Status Register via their own

status masks. The Status Register/interrupt structure is hierarchical at 3 levels. The top level

Status Register accumulates the interrupt requests from a number of level-2 Status Registers.

Some of the level-2 Status Registers accumulate interrupt requests from level-3 Status Registers.

To respond to an interrupt originating from a level-3 Status Register, both the top level status and

the level-2 Status Registers must be read to determine the source of the interrupt.

The Power Control function includes a Clock Control register, and 3 Enable registers. The Clock

Control register selects the master crystal frequency (12.288MHz or 15.36MHz), the signal routed

to the CLKOUT pin (Clock In or 1.536MHz) and allows the master crystal oscillator to be disabled

for complete power down applications. A hardware reset must be issued to re-enable the

oscillator. The Clock Enable register can disable the system clock to individual blocks when not

required thus saving power. The Tone and Audio Enable registers allow selective control of the

analogue functions, Codec and tone generator/decoder, progressively reducing power

consumption as un-used functions are disabled.

A Power Control Status register is available which indicates external “wake-up” events on the ST

and IOM busses. Any activity on the ST bus will trigger an ST wake-up interrupt (if the interrupt is

enabled with the appropriate masks), while the IOMRx pin (DU in TE applications) being pulled

low will trigger an IOM wake-up interrupt. These interrupts will be generated even if the IOM and

ST master clocks have been disabled.

The ‘Power Control Status’ register also contains 2 flags, ‘CI0 Channel Idle’ and ‘IOM

Deactivated’ that indicate when the IOM bus can be safely deactivated. The ‘CI0 Channel Idle’

© 2001 Consumer Microcircuits Limited

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