CL-PS6700-VC-A Просмотр технического описания (PDF) - Cirrus Logic

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CL-PS6700-VC-A

Low-Power PC Card Controller for the CL-PS7111

Cirrus Logic 

CL-PS6700

Low-Power PC Card Controller

2.1.1 Address/Data Bus Signals (cont.)

Signal

Type

Power

Source

Description

MD[15:0] I/O

(cont.)

sys Data Phase: If a write transfer is indicated (during the address phase), write data appears in the

third clock (also a word write, during the fourth clock) of Chip Enable. For register read transfers, a

two-clock data phase follows the two clocks of address phase after a one clock bus turnaround

cycle. For card reads, the data phase is deferred until card data has been collected as signaled by

PRDY; the data phase is initiated by a second assertion of PCE_L, and the CL-PS6700 drives this

bus with read data in the clock following the assertion of PCE_L (if a word read, during the second

clock following PCE_L).

The data phase of MD[15:0] carries the transfer size and space required for the data (see Table 2-2

and Table 2-3). SLOT[1:0] is a space reserved for future expansion.

MD[15]

SIZE[1:0] SLOT[1:0] SPACE[1:0]

MD[0]

A[25:16]

MD[15]

1st Clock of Address Phase

A[15:0]

MD[0]

2nd Clock of Address Phase

Table 2-2. Transfer Size

SIZE[1:0] Number of bytes

00

1

11

4

Table 2-3. Area Accessed

SPACE[1:0] Area Accessed

00

Attribute space

01

I/O space

10

Common memory

11

CL-PS6700 register

space

CIRRUS LOGIC CONFIDENTIAL, NDA REQUIRED

November 1997

PRELIMINARY DATA BOOK v1.0

11

PIN DESCRIPTIONS

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