CL-PD6833 Просмотр технического описания (PDF) - Cirrus Logic
Номер в каталоге
Компоненты Описание
Список матч
CL-PD6833 Datasheet PDF : 216 Pages
| |||
CL-PD6833
PCI-to-CardBus Host Adapter
Table 2-2. Socket Interface Pins (cont.)
Pin Name1
Description2
Pin Number
Qty. I/O Pwr. Drive
Socket A Socket B
SOCKET_VCC Connect these pins to the VCC supply of
the socket (pins 17 and 51 of the respec-
tive PC Card 16 socket). These pins can
be 0, 3.3, or 5 V, depending on card pres-
ence, card type, and system configuration.
The socket interface outputs (listed in this
117, 98, 60
200, 160,
143
3 PWR
–
–
table, Table 2-2) operate at the voltage
applied to these pins, independent of the
voltage applied to other CL-PD6833 pin
groups.
1 To differentiate the sockets in the pin diagram, all socket-specific pins have either A_ or B_ prepended to the pin names indi-
cated. For example, A_A[25:0] and B_A[25:0] are the independent address buses to the sockets.
2 When a socket is configured as an ATA drive interface, socket interface pin functions change. See Chapter 14.
Table 2-3. Power Control and General Interface Pins
Pin Name
SPKR_OUT*
/GPIO3‡
Description
Pin Number Qty. I/O Pwr. Drive
Speaker Output: This output can be used as a
digital output to a speaker to allow a system to
support PC Card 16 fax/modem/voice and
audio sound output. This output is enabled by
setting the socket’s Misc Control 1 register bit 4
to ‘1’ (for the socket whose speaker signal is to
be directed from BVD2/-SPKR/-LED to this pin).
This pin is used for configuration information
during hardware reset. Refer to Misc Control 3
128
register bit 0.
General-Purpose Input/Output 3: This pin can
also be used for either input or output under the
control of the GPIO Input Control and GPIO
Output Control registers (see also the Pin
Multiplex Control 0 register at memory offset
914h). This pin is grouped with and powered
from the +5V pins.
1
I/O
1
8 mA
June 1998
ADVANCE DATA BOOK v0.3
21
PIN INFORMATION
Share Link: 