CDP18523 Просмотр технического описания (PDF) - Intersil

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CDP18523

High-Reliability Byte-Wide Input/Output Port

Intersil 

CDP1852/3, CDP1852C/3

Block Diagram of CDP1852/3

1

CSI/CSI†

CS2 13

MODE 2

CLOCK 11

CLEAR 14

DEVICE

SELECT

DECODE

CONTROL 23

LOGIC

SR/SR†

24 VDD

12

VSS

DI0 3

DI1 5

DI2 7

DI3 9

DI4 16

DI5 18

DI6 20

DI7 22

RESET CLOCK

8-BIT

DATA

REGISTER

ENABLE

THREE-

STATE

OUTPUT

DRIVERS

† POLARITY DEPENDS ON MODE

MODE = 0 MODE = 1

P1

CSI

CSI

P23

SR

SR

4 DO0

6 DO1

8 DO2

10 DO3

15 DO4

17 DO5

19 DO6

21 DO7

CS2

13

CSI/CSI

1

MODE

2

CLEAR

14

FIGURE 1.

S

DQ

VSS

SERVICE

R

REQUEST

CL LATCH

CLOCK

11

DI0

P

3

TG

N

P

TG

N

SR/SR

23

VDD

P

N

VSS

DO0

4

DI1

DO1

5

6

D17

DO7

22

21

FIGURE 2. CDP1852/3 LOGIC DIAGRAM

2

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