CDB5397 Просмотр технического описания (PDF) - Cirrus Logic
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CDB5397 Datasheet PDF : 40 Pages
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CS5396 CS5397
LRCK
Left
Right
SCLK
SDATA
24 23 9 8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 24 23 9 8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 24 23
MASTER
24-Bit Left Justified Data
Data Valid on Rising Edge of 64x SCLK
MCLK equal to 256x Fs
SLAVE
24-Bit Left Justified Data
Data Valid on Rising Edge of SCLK
MCLK equal to 256x Fs
Figure 4. Control Port Mode, Serial Data. Left Justified. 64x Oversampling Mode
The peak signal level bits are available only if Bit 6 of Byte 7 is set.
LRCK
Left
Right
SCLK
SDATA
24 23 9 8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 24 23 9 8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 24 23
MASTER
I2S 24-Bit Data
Data Valid on Rising Edge of 64x SCLK
MCLK equal to 256x Fs
SLAVE
I2S 24-Bit Data
Data Valid on Rising Edge of SCLK
MCLK equal to 256x Fs
Figure 5. Control Port Mode, Serial Data. I2S Compatible. 64x Oversampling Mode.
The peak signal level bits are available only if Bit 6 of Byte 7 is set.
LRCK
Left
SCLK
SDATA
23 22 1 0 P7 P6 P5 P4 P3 P2 P1 P0
Right
23 22 1 0 P7 P6 P5 P4 P3 P2 P1 P0
MASTER
24-Bit Left Justified Data
Data Valid on Rising Edge of 128x SCLK
MCLK equal to 512x Fs
SLAVE
24-Bit Left Justified Data
Data Valid on Rising Edge of SCLK
MCLK equal to 512x Fs
Figure 6. Control Port Mode, Serial Data. Left Justified. 128x Oversampling Mode
The peak signal level bits are available only if Bit 6 of Byte 7 is set.
23 22
LRCK
Left
Right
SCLK
SDATA
23 22
1 0 P7 P6 P5 P4 P3 P2 P1 P0
23 22 1 0 P7 P6 P5 P4 P3 P2 P1 P0
MASTER
I2S 24-Bit Data
Data Valid on Rising Edge of 128x SCLK
MCLK equal to 512x Fs
SLAVE
I2S 24-Bit Data
Data Valid on Rising Edge of SCLK
MCLK equal to 512x Fs
Figure 7. Control Port Mode, Serial Data. I2S Compatible. 128x Oversampling Mode.
The peak signal level bits are available only if Bit 6 of Byte 7 is set.
23 22
16
DS229PP2
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