CS4364-CQZR(2008) Просмотр технического описания (PDF) - Cirrus Logic
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CS4364-CQZR Datasheet PDF : 50 Pages
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CS4364
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT
(Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 30 pF)
Parameter
SCL Clock Frequency
RST Rising Edge to Start
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
(Note 16)
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
Fall Time SCL and SDA
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling
Symbol
fscl
tirs
tbuf
thdst
tlow
thigh
tsust
thdd
tsud
trc, trc
tfc, tfc
tsusp
tack
Min
-
500
4.7
4.0
4.7
4.0
4.7
0
250
-
-
4.7
300
Max
100
-
-
-
-
-
-
-
-
1
300
-
1000
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
Notes:
16. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
RST
t irs
Stop
S tart
R epeated
S tart
SDA
t buf
t hdst
t high
t hdst
tf
SCL
t low
t hdd
t sud
t sust
tr
Figure 4. Control Port Timing - I²C Format
Stop
t susp
16
DS619F1
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