CS42L55 Просмотр технического описания (PDF) - Cirrus Logic

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CS42L55

Ultra Low Power, Stereo CODEC w/Class H Headphone Amp

Cirrus Logic 

SWITCHING SPECIFICATIONS - CONTROL PORT

Inputs: Logic 0 = GND = AGND, Logic 1 = VL, SDA CL = 30 pF.

Parameter

Symbol

Min

SCL Clock Frequency

fscl

-

RESET Rising Edge to Start

tirs

500

Bus Free Time Between Transmissions

tbuf

4.7

Start Condition Hold Time (prior to first clock pulse)

thdst

4.0

Clock Low time

tlow

4.7

Clock High Time

thigh

4.0

Setup Time for Repeated Start Condition

tsust

4.7

SDA Hold Time from SCL Falling

(Note 19)

thdd

0

SDA Setup time to SCL Rising

tsud

250

Rise Time of SCL and SDA

trc

-

Fall Time SCL and SDA

tfc

-

Setup Time for Stop Condition

tsusp

4.7

Acknowledge Delay from SCL Falling

tack

300

Notes:

19. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.

CS42L55

Max

100

-

-

-

-

-

-

-

-

1

300

-

1000

Unit

kHz

ns

µs

µs

µs

µs

µs

µs

ns

µs

ns

µs

ns

RESET

t irs

Stop

Start

Repeated

Start

SDA

t buf

t hdst

t high

t hdst

tf

SCL

t low t hdd

t sud

t sust

tr

Figure 7. I²C Control Port Timing

Stop

t susp

18

DS773F1

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