CS4265-DNZR Просмотр технического описания (PDF) - Cirrus Logic

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CS4265-DNZR

104 dB, 24-Bit, 192 kHz Stereo Audio CODEC

Cirrus Logic 

CS4265

Figure 42.Consumer Output Circuit (VD = 5 V) ........................................................................................ 51

Figure 43.TTL/CMOS Output Circuit ......................................................................................................... 51

Figure 44.Channel Status Data Buffer Structure ....................................................................................... 52

Figure 45.Flowchart for Writing the E Buffer ............................................................................................. 53

LIST OF TABLES

Table 1. Speed Modes .............................................................................................................................. 24

Table 2. Common Clock Frequencies ....................................................................................................... 24

Table 3. Slave Mode Serial Bit Clock Ratios ............................................................................................. 25

Table 4. Device Revision .......................................................................................................................... 35

Table 5. Freeze-able Bits .......................................................................................................................... 35

Table 6. DAC Digital Interface Formats .................................................................................................... 36

Table 7. De-Emphasis Control .................................................................................................................. 37

Table 8. Functional Mode Selection .......................................................................................................... 37

Table 9. ADC Digital Interface Formats .................................................................................................... 38

Table 10. MCLK Frequency ...................................................................................................................... 38

Table 11. DAC SDIN Source Selection ..................................................................................................... 39

Table 12. Example Gain and Attenuation Settings ................................................................................... 39

Table 13. PGA Soft Cross or Zero Cross Mode Selection ........................................................................ 40

Table 14. Analog Input Selection .............................................................................................................. 40

Table 15. Digital Volume Control Example Settings ................................................................................. 41

Table 16. DAC Soft Cross or Zero Cross Mode Selection ........................................................................ 42

Table 17. Transmitter Digital Interface Formats ........................................................................................ 44

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DS657F2

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