CD40182 Просмотр технического описания (PDF) - Intersil
Номер в каталоге
Компоненты Описание
Список матч
CD40182 Datasheet PDF : 9 Pages
| |||
CD40182BMS
(16) CD40181BMS
Cn
GP
Cn
GP
Cn
GP
Cn
GP
Cn
GP
Cn
GP
Cn
GP
Cn
GP
G0 P0 Cn + x
Cn
G1 P1 Cn + y G2 P2
CD40182BMS
Cn + z G3 P3
GP
G0 P0 Cn + x G1 P1 Cn + y G2 P2 Cn + z G3 P3
Cn
CD40182BMS
Cn
GP
G0 P0
Cn
G0 P0 Cn + x
Cn
CD40182BMS
FIGURE 10. 64-BIT FULL CARRY LOOK-AHEAD ALU IN 3 LEVELS
CD40181BMS
G1 P1 Cn + y
Cn Cn + 4 Cn Cn + 4
Cn
GP
Cn
GP
Cn
GP
Cn Cn+4 Cn Cn+4
Cn
GP
Cn
GP
G0 P0 Cn + x G1 P1 Cn + y G2 P2 Cn + z G3 P3
Cn
CD40182BMS
GP
G0 P0 Cn + x G1 P1 Cn + y
Cn
CD40181BMS
FIGURE 11. COMBINED TWO-LEVEL LOOK-AHEAD AND RIPPLE-CARRY ALU
Chip Dimensions and Pad Layout
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
The photographs and dimensions of each CMOS chip represent a chip when
it is part of the wafer. When the wafer is separated into individual chips, the an-
gle of cleavage may vary with respect to the chip face for different chips. The
actual dimensions of the isolated chip, therefore, may differ slightly from the
nominal dimensions shown. The user should consider a tolerance of -3 mils to
+16 mils applicable to the nominal dimensions shown.
Dimension in parenthesis are in millimeters and are derived from the basic inch
dimensions as indicated. Grid graduations are in mils (10-3 inch).
7-1418
Share Link: 