CAT5140 Просмотр технического описания (PDF) - ON Semiconductor

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CAT5140

Single Channel 256 Tap DPP™ with Integrated EEPROM and I2C Control

ON Semiconductor 

CAT5140

SCL

SDA

Start

Condition

Figure 2. Start and STOP Timing

Stop

Condition

tF

SCL

tSU:STA

SDA IN

SDA OUT

tLOW

tHIGH

tHD:STA

tHD:DAT

tAA

tR

tSU:DAT

tDH

Figure 3. Bus Timing

SCL from

Master

Bus Release Delay (Transmitter)

1

8

9

tSU:STO

tBUF

Bus Release

Delay (Receiver)

Data Output

from Transmitter

Data Output

from Receiver

Start

ACK Delay (≤ tAA)

Figure 4. Acknowledge Timing

ACK Setup (≥ tSU:DAT)

SCL

SDA IN

WP

Start

CLK1

tSU:WP

Figure 5. WP Timing

Stop

tHD:STO, tHD:STO:NV

tHD:WP

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