CA3282 Просмотр технического описания (PDF) - Intersil
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CA3282 Datasheet PDF : 10 Pages
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Timing Diagrams (Continued)
CA3282
CE
(INPUT)
(2)
(4)
(1)
(13)
(12)
(3)
SCK
(INPUT)
LAST BIT
(5)
HIGH
TRANSMITTED
MISO Z
(OUTPUT)
D70
D60
(8)
(10)
MOSI
(INPUT)
D71
D61
(6) (7)
D10
(11)
(9)
D11
FAULT-INDUCED
TURN-OFF
DRIVER
OUTPUT
OLD
FIGURE 1B. SPI TIMING DIAGRAM
NEW
tPHL
tPLH
tUD
RESET
CE
SCK
MOSI
7
6
5
4
3
2
1
0
MISO
7
6
5
4
3
2
1
0
OUTPUTS
OLD
NEW
RESET
FAULTS
FIGURE 2. BYTE TIMING DIAGRAM WITH ASYNCHRONOUS RESET
Signal Descriptions
Power Output Drivers, Output 0 - Output 7 - The input and
output bits corresponding to Output 0 thru Output 7 are
transmitted and received most significant bit (MSB) first via
the SPI bus. The outputs are provided with current limiting
and voltage sense functions for fault indication and protec-
tion. The nominal load current for these outputs is 500mA,
with current limiting set to a minimum of 1.05A. An on-chip
clamp circuit capable of handling 500mA is provided at each
output for clamping inductive loads.
RESET - Active low reset input. When this input line is low,
the shift register and output latches are configured to turn off
all output drivers. A power on clear function may be imple-
mented by connecting this pin to VDD with an external resis-
tor, and to VSS with an external capacitor. In any case, this
pin must not be left floating.
CE - Active low chip enable. Data is transferred from the shift
register to the outputs on the rising edge of this signal. The
falling edge of CE loads the shift register with the output volt-
age sense bits coming from the output stages. The output
driver for the MISO pin is enabled when this pin is low. CE
must be a logic low prior to the first serial clock (SCK) and
must remain low until after the last (eighth) serial clock cycle.
A low level on CE also activates an internal disable circuit
used for unlatching output states that are in a fault mode as
4
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