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VP306S Просмотр технического описания (PDF) - Mitel Networks

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VP306S
Mitel
Mitel Networks Mitel
VP306S Datasheet PDF : 85 Pages
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VP305/6
VIT E R B I
COAR S E
B IT
E R R OR
COU NT
DRAFT - PRELIMINARY DATA
V M E R R [7 :0 ]
0
0
DAT A B IT S
VE R R
Fig. 9. Viterbi error count coarse indication.
1.4. The De-interleaver block.
Before transmission, the data bytes are interleaved with each other in a cyclic pattern of twelve.
This ensures the bytes are spaced out, so that successive message bytes are transmitted with a
separation of at least 12 bytes. This system is used to avoid the possibility of a noise spike
corrupting a group of consecutive message bytes. The diagram below shows conceptually how
the convolutional de-interleaving system works. The synchronisation byte is always loaded into the
First-In-First-Out (FIFO) memory in branch 0. The switch is operated at regular byte intervals to
write successively received bytes into the next branch. After 12 bytes have been received, byte 13
is written next to the synchronisation byte in branch 0, etc. Only when the FIFOs are full, will the
read out of the 204 byte message be enabled. On the VP305/6, this function is realised in random
access memory (RAM) with some spare capacity to avoid messages being over written before
they are read out.
The duplication or disclosure of data contained on this sheet is subject to the restrictions
on the title page of this document.
16

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