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VP306SCG

Satellite Channel Decoder

Mitel Networks 

ERROR

COUNT

VERRC[15:0]

DRAFT - PRELIMINARY DATA

VP305/6

0

0

VITEP[23:0]

DATA BITS

IRQ

Fig. 8. Viterbi error count measurement.

Figure 8 above shows the bit errors rising until the maximum programmed value of VITEP[23:0] is

reached, when an interrupt is generated on the IRQ line to advise the host microprocessor that a

new value of bit error count has been loaded into the VERRC[15:0] register. The IRQ line will go

high when the IE_FEC register is read by the host microprocessor.

The error count may be expressed as a ratio:

VERRC[15:0]

VITEP[23:0]

.

1.3.2. Viterbi error count coarse indication.

To assist in the process of aligning the receiver dish aerial, a coarse indication of the number of bit

errors being received can be provided by monitoring the VERR line with the following set up

conditions.

The frequency of the output wave form will be a function of the bit error count (triggering the

maximum value programmed into the VI MAX ERR register (VMERR[7:0])) and the dish alignment

on the satellite. This VERR mode is enabled by setting the INTVIS bit in the TEST2 register.

Figure 9 below shows the bit errors rising to the maximum programmed value and triggering a

change of state on the VERR line.

The duplication or disclosure of data contained on this sheet is subject to the restrictions

on the title page of this document.

15

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