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VP306SCG

Satellite Channel Decoder

Mitel Networks 

VP305/6

DRAFT - PRELIMINARY DATA

1.2.1. Input requirements.

The data input is digitised six bit I and Q channel data in the form of either binary format or offset

2's complement data. The QPSK phase constellation representation is shown below.

I=1

Q=0

Q

I=0

Q=0

I

I=1

I=0

Q=1

Q=1

Fig. 4. QPSK constellation.

1.2.3. Matched filters

The Decimation filter and matched filter together have a 0.35 roll-off square-root-raised-cosine

frequency response as in reference 1.

1.2.4. Decimation filters

In order to adjust to the wide range of symbol rates (5 to 30Msym/s), the I and Q data in may be

decimated by varying degrees. The system also allows for the ADC sample clock to be adjusted to

within the range 30 to 62MHz.

The sample rate at the input to the matched filter is equal to twice the symbol rate, 2Rs. The

SYM_DR bits in the SYM_CONFIG register can be programmed to allow for the following filtered

symbol rates at the input to the VP305/6:

2Rs, 3Rs, 4Rs, where Rs = symbol rate.

IIN

SYM_RATIO

unfiltered

QIN

Decimation

SYM_RP

filtered

Decimation

Matched

Filter

Fig. 5. Symbol filtering.

The SYM_RATIO register allows the input symbol rate to be extended further to cover 6Rs, 8Rs,

12Rs, 16Rs, 24Rs, 32Rs, 48Rs and 64Rs unfiltered decimation rates.

The number of samples / Symbol (M) can be calculated from the formula:

M = (SYM_DR over sample rate) * (2SYM_RATIO)

The range of values of M is shown in the table below.

The duplication or disclosure of data contained on this sheet is subject to the restrictions

on the title page of this document.

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