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IDT72V3690L10PFI

3.3 VOLT HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO

Integrated Device Technology 

IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO

1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

DESCRIPTION (CONTINUED)

of RCLK when REN is asserted. An Output Enable (OE) input is provided for

three-state control of the outputs.

The frequencies of both the RCLK and the WCLK signals may vary from 0

to fMAX with complete independence. There are no restrictions on the frequency

of the one clock input with respect to the other.

There are two possible timing modes of operation with these devices: IDT

Standard mode and First Word Fall Through (FWFT) mode.

In IDT Standard mode, the first word written to an empty FIFO will not appear

on the data output lines unless a specific read operation is performed. A read

operation, which consists of activating REN and enabling a rising RCLK edge,

will shift the word from internal memory to the data output lines.

In FWFT mode, the first word written to an empty FIFO is clocked directly

to the data output lines after three transitions of the RCLK signal. A REN does

not have to be asserted for accessing the first word. However, subsequent

words written to the FIFO do require a LOW on REN for access. The state of

the FWFT/SI input during Master Reset determines the timing mode in use.

For applications requiring more data storage capacity than a single FIFO

can provide, the FWFT timing mode permits depth expansion by chaining FIFOs

in series (i.e. the data outputs of one FIFO are connected to the corresponding

data inputs of the next). No external logic is required.

These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready),

FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable

Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF and FF

functions are selected in IDT Standard mode. The IR and OR functions are

selected in FWFT mode. HF, PAE and PAF are always available for use,

irrespective of timing mode.

PAE and PAF can be programmed independently to switch at any point in

memory. Programmable offsets determine the flag switching threshold and can

be loaded by two methods: parallel or serial. Eight default offset settings are also

provided, so that PAE can be set to switch at a predefined number of locations

from the empty boundary and the PAF threshold can also be set at similar

predefined values from the full boundary. The default offset values are set during

Master Reset by the state of the FSEL0, FSEL1, and LD pins.

For serial programming, SEN together with LD on each rising edge of

WCLK, are used to load the offset registers via the Serial Input (SI). For parallel

programming, WEN together with LD on each rising edge of WCLK, are used

to load the offset registers via Dn. REN together with LD on each rising edge

of RCLK can be used to read the offsets in parallel from Qn regardless of whether

serial or parallel offset loading has been selected.

During Master Reset (MRS) the following events occur: the read and write

pointers are set to the first location of the FIFO. The FWFT pin selects IDT

Standard mode or FWFT mode.

The Partial Reset (PRS) also sets the read and write pointers to the first

location of the memory. However, the timing mode, programmable flag

programming method, and default or programmed offset settings existing before

Partial Reset remain unchanged. The flags are updated according to the timing

mode and offsets in effect. PRS is useful for resetting a device in mid-operation,

when reprogramming programmable flags would be undesirable.

It is also possible to select the timing mode of the PAE (Programmable Almost-

Empty flag) and PAF (Programmable Almost-Full flag) outputs. The timing

modes can be set to be either asynchronous or synchronous for the PAE and

PAF flags.

If asynchronous PAE/PAF configuration is selected, the PAE is asserted

LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOW-

to-HIGH transition of WCLK. Similarly, the PAF is asserted LOW on the LOW-

to-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH

transition of RCLK.

If synchronous PAE/PAF configuration is selected , the PAE is asserted and

updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is

PARTIAL RESET (PRS) MASTER RESET (MRS)

WRITE CLOCK (WCLK)

WRITE ENABLE (WEN)

LOAD (LD)

(x36, x18, x9) DATA IN (D0 - Dn)

SERIAL ENABLE(SEN)

FIRST WORD FALL THROUGH/SERIAL INPUT

(FWFT/SI)

FULL FLAG/INPUT READY (FF/IR)

PROGRAMMABLE ALMOST-FULL (PAF)

IDT

72V3640

72V3650

72V3660

72V3670

72V3680

72V3690

72V36100

72V36110

READ CLOCK (RCLK)

READ ENABLE (REN)

OUTPUT ENABLE (OE)

(x36, x18, x9) DATA OUT (Q0 - Qn)

RETRANSMIT (RT)

EMPTY FLAG/OUTPUT READY (EF/OR)

PROGRAMMABLE ALMOST-EMPTY (PAE)

HALF-FULL FLAG (HF)

BIG-ENDIAN/LITTLE-ENDIAN (BE)

INTERSPERSED/

NON-INTERSPERSED PARITY (IP)

INPUT WIDTH (IW) BUS- OUTPUT WIDTH (OW)

MATCHING

(BM)

4667 drw 03

Figure 1. Single Device Configuration Signal Flow Diagram

3

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