IDT72V3690L7.5PF Просмотр технического описания (PDF) - Integrated Device Technology

Номер в каталоге

Компоненты Описание

Список матч

IDT72V3690L7.5PF

3.3 VOLT HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO

Integrated Device Technology 

IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO

1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

OPTIONAL CONFIGURATIONS

WIDTH EXPANSION CONFIGURATION

Word width may be increased simply by connecting together the control

signals of multiple devices. Status flags can be detected from any one device.

The exceptions are the EF and FF functions in IDT Standard mode and the IR

and OR functions in FWFT mode. Because of variations in skew between RCLK

and WCLK, it is possible for EF/FF deassertion and IR/OR assertion to vary

by one cycle between FIFOs. In IDT Standard mode, such problems can be

avoided by creating composite flags, that is, ANDing EF of every FIFO, and

separately ANDing FF of every FIFO. In FWFT mode, composite flags can be

created by ORing OR of every FIFO, and separately ORing IR of every FIFO.

Figure 22 demonstrates a width expansion using two IDT72V3640/

72V3650/72V3660/72V3670/72V3680/72V3690/72V36100/72V36110 de-

vices. D0 - D35 from each device form a 72-bit wide input bus and Q0-Q35 from

each device form a 72-bit wide output bus. Any word width can be attained by

adding additional IDT72V3640/72V3650/72V3660/72V3670/72V3680/

72V3690/72V36100/72V36110 devices.

PARTIAL RESET (PRS)

MASTER RESET (MRS)

FIRST WORD FALL THROUGH/

SERIAL INPUT (FWFT/SI)

RETRANSMIT (RT)

DATA IN

m+n

D0 - Dm m

WRITE CLOCK (WCLK)

WRITE ENABLE (WEN)

LOAD (LD)

(1)

GATE

FULL FLAG/INPUT READY (FF/IR) #1

FULL FLAG/INPUT READY (FF/IR) #2

PROGRAMMABLE (PAF)

HALF-FULL FLAG (HF)

Dm+1 - Dn

n

IDT

72V3640

72V3650

72V3660

72V3670

72V3680

72V3690

72V36100

72V36110

FIFO

#1

m

IDT

72V3640

72V3650

72V3660

72V3670

72V3680

72V3690

72V36100

72V36110

FIFO

#2

READ CLOCK (RCLK)

READ ENABLE (REN)

OUTPUT ENABLE (OE)

PROGRAMMABLE (PAE)

EMPTY FLAG/OUTPUT READY (EF/OR) #1

EMPTY FLAG/OUTPUT READY (EF/OR) #2

n Qm+1 - Qn

m+n

DATA OUT

(1)

GATE

Q0 - Qm

4667 drw 28

NOTES:

1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.

2. Do not connect any output control signals directly together.

3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.

Figure 23. Block Diagram of 1,024 x 72, 2,048 x 72, 4,096 x 72, 8,192 x 72, 16,384 x 72, 32,768 x 72, 65,536 x 72 and 131,072 x 72 Width Expansion

DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)

The IDT72V3640 can easily be adapted to applications requiring depths

greater than 1,024, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660,

8,192 for the IDT72V3670, 16,384 for the IDT72V3680, 32,768 for the

IDT72V3690, 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110

with an 18-bit bus width. In FWFT mode, the FIFOs can be connected in series

(the data outputs of one FIFO connected to the data inputs of the next) with no

external logic necessary. The resulting configuration provides a total depth

equivalent to the sum of the depths associated with each single FIFO. Figure

23 shows a depth expansion using two IDT72V3640/72V3650/72V3660/

72V3670/72V3680/72V3690/72V36100/72V36110 devices.

Care should be taken to select FWFT mode during Master Reset for all FIFOs

in the depth expansion configuration. The first word written to an empty

configuration will pass from one FIFO to the next ("ripple down") until it finally

appears at the outputs of the last FIFO in the chain – no read operation is

necessary but the RCLK of each FIFO must be free-running. Each time the data

word appears at the outputs of one FIFO, that device's OR line goes LOW,

enabling a write to the next FIFO in line.

34

Share Link: