IDT72V3650L15PF Просмотр технического описания (PDF) - Integrated Device Technology

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IDT72V3650L15PF

3.3 VOLT HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO

Integrated Device Technology 

IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO

1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

RCLK

tENS

1

2

3

tENH

REN

tA

Q0 - Qn

Wx

Wx+1

tA

W0

tSKEW2

tA

tA

W1(3)

W2(3)

tA

W3

WCLK

WEN

tRTS

tENS

1

2

tENH

RT

EF

tPAES

PAE

tHF

HF

PAF

tPAFS

4667 drw 18

NOTES:

1. If the part is empty at the point of Retransmit, the empty flag (EF) will be updated based on RCLK (Retransmit clock cycle), valid data will also appear on the output.

2. OE = LOW.

3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.

4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.

D = 1,024 for IDT72V3640, 2,048 for IDT72V3650, 4,096 for IDT72V3660, 8,192 for IDT72V3670, 16,384 for the IDT72V3680, 32,768 for the IDT72V3690, 65,536 for the IDT72V36100

and 131,072 for the IDT72V36110.

5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.

6. RM is set LOW during MRS.

Figure 13. Zero Latency Retransmit Timing (IDT Standard Mode)

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