IDT72V3660L7.5PFI Просмотр технического описания (PDF) - Integrated Device Technology

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IDT72V3660L7.5PFI

3.3 VOLT HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO

Integrated Device Technology 

WCLK

tENS

tENH

WEN

tDS

tDH

D0 - D17

WD

1

2

tSKEW1(1)

(2)

tSKEW2

RCLK

REN

OE

Q0 - Q17

tENS

1

tENS

tOHZ

W1

tOE

tA

W1

W2

tA

W3

Wm+2

tA

W[m+3]

W[m+4]

tA

W[D-1 ] W[D-1 ]

tA

W[D-n-1]

W[D-n]

W[D-n+1] W[D-n+2]

tA

W[D-1]

OR

PAE

tPAES

WD

tREF

HF

tHF

PAF

tWFF

IR

tWFF

tPAFS

4667 drw 15

NOTES:

1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that IR will go LOW after one WCLK cycle plus tWFF. If the time between the rising edge of RCLK and the rising edge of WCLK is less than

tSKEW1, then the IR assertion may be delayed one extra WCLK cycle.

2. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH after one WCLK cycle plus tPAFS. If the time between the rising edge of RCLK and the rising edge of WCLK is less than

tSKEW2, then the PAF deassertion may be delayed one extra WCLK cycle.

3. LD = HIGH

4. n = PAE Offset, m = PAF offset and D = maximum FIFO depth.

5. D = 1,025 for IDT72V3640, 2,049 for IDT72V3650, 4,097 for IDT72V3660, 8,193 for IDT72V3670, 16,385 for the IDT72V3680, 32,769 for the IDT72V3690, 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.

Figure 10. Read Timing (First Word Fall Through Mode)

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