IDT72V3690L15PFI Просмотр технического описания (PDF) - Integrated Device Technology

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IDT72V3690L15PFI

3.3 VOLT HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO

Integrated Device Technology 

WCLK

WEN

D0 - D17

tENS

tDS

W1

RCLK

tDH

W2

tSKEW1(1)

1

W3

2

1

tDS

tDS

tDS

W4

W[n +2]

W[n+3]

W[n+4]

W[D-1 ] W[D-1 ] W[D-1 ] W[D-m-2]

W[D-m-1]

W[D-m]

W[D-m+1] W[D-m+2]

W[D-1]

WD

tSKEW2(2)

3

1

2

tENH

REN

tA

Q0 - Q17

DATA IN OUTPUT REGISTER

W1

tREF

OR

PAE

tPAES

HF

PAF

IR

tHF

tPAFS

tWFF

4667 drw 14

NOTES:

1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that OR will go LOW after two RCLK cycles plus tREF. If the time between the rising edge of WCLK and the rising edge of RCLK is less than

tSKEW1, then OR assertion may be delayed one extra RCLK cycle.

2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH after one RCLK cycle plus tPAES. If the time between the rising edge of WCLK and the rising edge of RCLK is less than

tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.

3. LD = HIGH, OE = LOW

4. n = PAE offset, m = PAF offset and D = maximum FIFO depth.

5. D = 1,025 for IDT72V3640, 2,049 for IDT72V3650, 4,097 for IDT72V3660, 8,193 for IDT72V3670, 16,385 for the IDT72V3680, 32,769 for the IDT72V3690, 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.

6. First data word latency = tSKEW1 + 2*TRCLK + tREF.

Figure 9. Write Timing (First Word Fall Through Mode)

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