IDT72V3670L7.5PFI Просмотр технического описания (PDF) - Integrated Device Technology

Номер в каталоге

Компоненты Описание

Список матч

IDT72V3670L7.5PFI

3.3 VOLT HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO

Integrated Device Technology 

IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO

1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

WCLK

D0 - Dn

FF

t SKEW1 (1)

NO WRITE

1

t CLKH

2

t DS

t CLK

tCLKL

t DH

DX

t WFF

t WFF

(1)

t SKEW1

NO WRITE

1

2

t DS

t DH

t WFF

DX+1

t WFF

WEN

RCLK

REN

Q0 - Qn

t ENS

t ENH

tA

DATA IN OUTPUT REGISTER

t ENS

DATA READ

t ENH

tA

NEXT DATA READ

4667 drw 12

NOTES:

1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle pus tWFF). If the time between

the rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.

2. LD = HIGH, OE = LOW, EF = HIGH

Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)

RCLK

tENS

REN

EF

Q0 - Qn

OE

WCLK

WEN

D0 - Dn

tENH

tREF

1

NO OPERATION

tCLKH

2

NO OPERATION

tREF

tCLK

tCLKL

tENS

tENH

tA

tOLZ

tOE

tSKEW1(1)

LAST WORD

tOHZ

tA

LAST WORD

tOLZ

tENS

tENH

tDS

tDH

D0

tENS

tENH

tDS

tDH

D1

tENS

D0

tENH

tREF

tA

D1

4667 drw 13

NOTES:

1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the rising edge

of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle.

2. LD = HIGH.

3. First data word latency = tSKEW1 + 1*TRCLK + tREF.

Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)

24

Share Link: