IDT72V3650L10PFI Просмотр технического описания (PDF) - Integrated Device Technology

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IDT72V3650L10PFI

3.3 VOLT HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO

Integrated Device Technology 

IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO

1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

if EF was HIGH before setup. During this period, the internal read pointer is

initialized to the first location of the RAM array.

When EF goes HIGH, Retransmit setup is complete and read operations

may begin starting with the first location in memory. Since IDT Standard mode

is selected, every word read including the first word following Retransmit setup

requires a LOW on REN to enable the rising edge of RCLK. See Figure 11,

Retransmit Timing (IDT Standard Mode), for the relevant timing diagram.

If FWFT mode is selected, the FIFO will mark the beginning of the Retransmit

setup by setting OR HIGH. During this period, the internal read pointer is set

to the first location of the RAM array.

When OR goes LOW, Retransmit setup is complete; at the same time, the

contents of the first location appear on the outputs. Since FWFT mode is selected,

the first word appears on the outputs, no LOW on REN is necessary. Reading

all subsequent words requires a LOW on REN to enable the rising edge of

RCLK. See Figure 12, Retransmit Timing (FWFT Mode), for the relevant timing

diagram.

For either IDT Standard mode or FWFT mode, updating of the PAE, HF

and PAF flags begin with the rising edge of RCLK that RT is setup. PAE is

synchronized to RCLK, thus on the second rising edge of RCLK after RT is setup,

the PAE flag will be updated. HF is asynchronous, thus the rising edge of RCLK

that RT is setup will update HF. PAF is synchronized to WCLK, thus the second

rising edge of WCLK that occurs tSKEW after the rising edge of RCLK that RT

is setup will update PAF. RT is synchronized to RCLK.

The Retransmit function has the option of two modes of operation, either

“normal latency” or “zero latency”. Figure 11 and Figure 12 mentioned

previously, relate to “normal latency”. Figure 13 and Figure 14 show “zero

latency” retransmit operation. Zero latency basically means that the first data

word to be retransmitted, is placed onto the output register with respect to the

RCLK pulse that initiated the retransmit.

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