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IDT72V3680L10PFI

3.3 VOLT HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO

Integrated Device Technology 

IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO

1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

SERIAL PROGRAMMING MODE

If Serial Programming mode has been selected, as described above, then

programming of PAE and PAF values can be achieved by using a combination

of the LD, SEN, WCLK and SI input pins. Programming PAE and PAF proceeds

as follows: when LD and SEN are set LOW, data on the SI input are written,

one bit for each WCLK rising edge, starting with the Empty Offset LSB and ending

with the Full Offset MSB. A total of 20 bits for the IDT72V3640, 22 bits for the

IDT72V3650, 24 bits for the IDT72V3660, 26 bits for the IDT72V3670, 28 bits

for the IDT72V3680, 30 bits for the IDT72V3690, 32 bits for the IDT72V36100

and 34 bits for the IDT72V36110. See Figure 15, Serial Loading of Program-

mable Flag Registers, for the timing diagram for this mode.

Using the serial method, individual registers cannot be programmed

selectively. PAE and PAF can show a valid status only after the complete set

of bits (for all offset registers) has been entered. The registers can be

reprogrammed as long as the complete set of new offset bits is entered. When

LD is LOW and SEN is HIGH, no serial write to the registers can occur.

Write operations to the FIFO are allowed before and during the serial

programming sequence. In this case, the programming of all offset bits does

not have to occur at once. A select number of bits can be written to the SI input

and then, by bringing LD and SEN HIGH, data can be written to FIFO memory

via Dn by toggling WEN. When WEN is brought HIGH with LD and SEN

restored to a LOW, the next offset bit in sequence is written to the registers via

SI. If an interruption of serial programming is desired, it is sufficient either to set

LD LOW and deactivate SEN or to set SEN LOW and deactivate LD. Once LD

and SEN are both restored to a LOW level, serial offset programming continues.

From the time serial programming has begun, neither programmable flag

will be valid until the full set of bits required to fill all the offset registers has been

written. Measuring from the rising WCLK edge that achieves the above criteria;

PAF will be valid after two more rising WCLK edges plus tPAF, PAE will be valid

after the next two rising RCLK edges plus tPAE plus tSKEW2.

It is only possible to read the flag offset values via the parallel output port Qn.

PARALLEL MODE

If Parallel Programming mode has been selected, as described above, then

programming of PAE and PAF values can be achieved by using a combination

of the LD, WCLK , WEN and Dn input pins. Programming PAE and PAF

proceeds as follows: LD and WEN must be set LOW. For x36 bit input bus width,

data on the inputs Dn are written into the Empty Offset Register on the first LOW-

to-HIGH transition of WCLK. Upon the second LOW-to-HIGH transition of

WCLK, data are written into the Full Offset Register. The third transition of WCLK

writes, once again, to the Empty Offset Register. For x18 bit input bus width,

data on the inputs Dn are written into the Empty Offset Register LSB on the first

LOW-to-HIGH transition of WCLK. Upon the 2nd LOW-to-HIGH transition of

WCLK data are written into the Empty Offset Register MSB. The third transition

of WCLK writes to the Full Offset Register LSB, the fourth transition of WCLK then

writes to the Full Offset Register MSB. The fifth transition of WCLK writes once

again to the Empty Offset Register LSB. A total of four writes to the offset registers

is required to load values using a x18 input bus width. For an input bus width

of x9 bits, a total of six write cycles to the offset registers is required to load values.

See Figure 3, Programmable Flag Offset Programming Sequence. See

Figure 16, Parallel Loading of Programmable Flag Registers, for the timing

diagram for this mode.

The act of writing offsets in parallel employs a dedicated write offset register

pointer. The act of reading offsets employs a dedicated read offset register

pointer. The two pointers operate independently; however, a read and a write

should not be performed simultaneously to the offset registers. A Master Reset

initializes both pointers to the Empty Offset (LSB) register. A Partial Reset has

no effect on the position of these pointers.

Write operations to the FIFO are allowed before and during the parallel

programming sequence. In this case, the programming of all offset registers does

not have to occur at one time. One, two or more offset registers can be written

and then by bringing LD HIGH, write operations can be redirected to the FIFO

memory. When LD is set LOW again, and WEN is LOW, the next offset register

in sequence is written to. As an alternative to holding WEN LOW and toggling

LD, parallel programming can also be interrupted by setting LD LOW and

toggling WEN.

Note that the status of a programmable flag (PAE or PAF) output is invalid

during the programming process. From the time parallel programming has

begun, a programmable flag output will not be valid until the appropriate offset

word has been written to the register(s) pertaining to that flag. Measuring from

the rising WCLK edge that achieves the above criteria; PAF will be valid after

two more rising WCLK edges plus tPAF, PAE will be valid after the next two rising

RCLK edges plus tPAE plus tSKEW2.

The act of reading the offset registers employs a dedicated read offset

register pointer. The contents of the offset registers can be read on the Q0-Qn

pins when LD is set LOW and REN is set LOW. For x36 output bus width, data

are read via Qn from the Empty Offset Register on the first LOW-to-HIGH

transition of RCLK. Upon the second LOW-to-HIGH transition of RCLK, data are

read from the Full Offset Register. The third transition of RCLK reads, once

again, from the Empty Offset Register. For x18 output bus width, a total of four

read cycles are required to obtain the values of the offset registers. Starting with

the Empty Offset Register LSB and finishing with the Full Offset Register MSB.

For x9 output bus width, a total of six read cycles must be performed on the offset

registers. See Figure 3, Programmable Flag Offset Programming Sequence.

See Figure 17, Parallel Read of Programmable Flag Registers, for the timing

diagram for this mode.

It is permissible to interrupt the offset register read sequence with reads or

writes to the FIFO. The interruption is accomplished by deasserting REN, LD,

or both together. When REN and LD are restored to a LOW level, reading of

the offset registers continues where it left off. It should be noted, and care should

be taken from the fact that when a parallel read of the flag offsets is performed,

the data word that was present on the output lines Qn will be overwritten.

Parallel reading of the offset registers is always permitted regardless of

which timing mode (IDT Standard or FWFT modes) has been selected.

RETRANSMIT OPERATION

The Retransmit operation allows data that has already been read to be

accessed again. There are 2 modes of Retransmit operation, normal latency

and zero latency. There are two stages to Retransmit: first, a setup procedure

that resets the read pointer to the first location of memory, then the actual

retransmit, which consists of reading out the memory contents, starting at the

beginning of memory.

Retransmit setup is initiated by holding RT LOW during a rising RCLK edge.

REN and WEN must be HIGH before bringing RT LOW. When zero latency is

utilized, REN does not need to be HIGH before bringing RT LOW. At least two words,

but no more than D - 2 words should have been written into the FIFO, and read

from the FIFO, between Reset (Master or Partial) and the time of Retransmit

setup. D = 1,024 for the IDT72V3640, 2,048 for the IDT72V3650, 4,096 for

the IDT72V3660, 8,192 for the IDT72V3670, 16,384 for the IDT72V3680,

32,768 for the IDT72V3690, 65,536 for the IDT72V36100 and 131,072 for the

IDT72V36110. In FWFT mode, D = 1,025 for the IDT72V2640, 2,049 for the

IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385

for the IDT72V3680, 32,769 for the IDT72V3690, 65,537 for the IDT72V36100

and 131,073 for the IDT72V36110.

If IDT Standard mode is selected, the FIFO will mark the beginning of the

Retransmit setup by setting EF LOW. The change in level will only be noticeable

15

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