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IDT72V3640L10PF

3.3 VOLT HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO

Integrated Device Technology 

IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO

1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

1st Parallel Offset Write/Read Cycle

D/Q8

EMPTY OFFSET REGISTER (PAE)

8 765432

D/Q0

1

1st Parallel Offset Write/Read Cycle

D/Q8

EMPTY OFFSET REGISTER (PAE)

8 765432

D/Q0

1

2nd Parallel Offset Write/Read Cycle

D/Q8

EMPTY OFFSET REGISTER (PAE)

16 15 14 13 12 11 10

D/Q0

9

2nd Parallel Offset Write/Read Cycle

D/Q8

EMPTY OFFSET REGISTER (PAE)

16 15 14 13 12 11 10

D/Q0

9

3rd Parallel Offset Write/Read Cycle

D/Q8

EMPTY OFFSET REGISTER (PAE)

D/Q0

17

3rd Parallel Offset Write/Read Cycle

D/Q8

FULL OFFSET REGISTER (PAF)

8 76543 2

D/Q0

1

4th Parallel Offset Write/Read Cycle

D/Q8

FULL OFFSET REGISTER (PAF)

876543 2

D/Q0

1

4th Parallel Offset Write/Read Cycle

D/Q8

FULL OFFSET REGISTER (PAF)

16 15 14 13 12 11 10

D/Q0

9

IDT72V3640/50/60/70/80/90/100  x9 Bus Width

5th Parallel Offset Write/Read Cycle

D/Q8

FULL OFFSET REGISTER (PAF)

16 15 14 13 12 11 10

D/Q0

9

6th Parallel Offset Write/Read Cycle

D/Q8

FULL OFFSET REGISTER (PAF)

D/Q0

17

IDT72V36110  x9 Bus Width

# of Bits Used:

10 bits for the IDT72V3640

11 bits for the IDT72V3650

12 bits for the IDT72V3660

13 bits for the IDT72V3670

14 bits for the IDT72V3680

15 bits for the IDT72V3690

16 bits for the IDT72V36100

17 bits for the IDT72V36110

Note: All unused bits of the

LSB & MSB are don’t care

4667 drw07a

Figure 3. Programmable Flag Offset Programming Sequence (Continued)

14

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