IDT72V3640L10PFI Просмотр технического описания (PDF) - Integrated Device Technology

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IDT72V3640L10PFI

3.3 VOLT HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO

Integrated Device Technology 

IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO

1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

LD WEN REN SEN WCLK RCLK

IDT72V3640

IDT72V3650

IDT72V3660

IDT72V3670

IDT72V3680

IDT72V3690

IDT72V36100

IDT72V36110

0

0

1

1

X

Parallel write to registers:

Empty Offset (LSB)

Empty Offset (MSB)

Full Offset (LSB)

Full Offset (MSB)

0

1

0

1

X

Parallel read from registers:

Empty Offset (LSB)

Empty Offset (MSB)

Full Offset (LSB)

Full Offset (MSB)

0

1

1

0

Serial shift into registers:

X

20 bits for the 72V3640

22 bits for the 72V3650

24 bits for the 72V3660

26 bits for the 72V3670

28 bits for the 72V3680

30 bits for the 72V3690

32 bits for the 72V36100

34 bits for the 72V36110

X

1

1

1

X

1 bit for each rising WCLK edge

Starting with Empty Offset (LSB)

Ending with Full Offset (MSB)

X

No Operation

1

0

X

X

X

Write Memory

1

X

0

X

X

1

1

1

X

X

X

Read Memory

No Operation

NOTES:

1. The programming method can only be selected at Master Reset.

2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.

3. The programming sequence applies to both IDT Standard and FWFT modes.

4667 drw 06

Figure 3. Programmable Flag Offset Programming Sequence

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