IDT72V04L15JI(2003) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT72V04L15JI
(Rev.:2003)

3.3 VOLT CMOS ASYNCHRONOUS FIFO 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9

Integrated Device Technology 

IDT72V01/72V02/72V03/72V04/72V05/72V06 3.3V ASYNCHRONOUS FIFO

512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 and 16,384 x 9

RS

W

R

EF

HF, FF

tRSC

tRS

tRSS

tRSS

tEFL

tHFH, tFFH

NOTES:

1. EF, FF, HF may change status during Reset, but flags will be valid at tRSC.

2. W and R = VIH around the rising edge of RS.

Figure 2. Reset

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

tRSR

3033 drw 04

R

Q0-Q8

W

D0-D8

tRC

tA

tRR

tRPW

tA

tRLZ

tWPW

tDV

DATA OUT VALID

tWC

tWR

tRHZ

DATA OUT VALID

tDS

tDH

DATA IN VALID

DATA IN VALID

Figure 3. Asynchronous Write and Read Operation

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LAST WRITE

IGNORED

WRITE

FIRST READ

ADDITIONAL FIRST

READS

WRITE

R

W

tWFF

FF

t RFF

Figure 4. Full Flag From Last Write to First Read

5

3033 drw 06

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