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IDT54FCT3574PYB

3.3V CMOS OCTAL D REGISTERS (3-STATE)

Integrated Device Technology 

IDT54/74FCT3574/3574A

3.3V CMOS OCTAL D REGISTERS (3-STATE)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TEST CIRCUITS AND WAVEFORMS

TEST CIRCUITS FOR ALL OUTPUTS

6V

V CC

Open

V IN

Pulse

Generator

V OUT

D.U.T.

GND

500Ω

50pF

500Ω

RT

CL

3095 drw 03

SWITCH POSITION

Test

Open Drain

Disable Low

Enable Low

Disable High

Enable High

All Other tests

Switch

6V

GND

Open

DEFINITIONS:

3095 lnk 08

CL= Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse

Generator.

SET-UP, HOLD AND RELEASE TIMES

PULSE WIDTH

DATA

INPUT

tSU

TIMING

INPUT

ASYNCHRONOUS CONTROL

PRESET

CLEAR

ETC.

SYNCHRONOUS CONTROL

PRESET

CLEAR

CLOCK ENABLE

tSU

ETC.

tH

tREM

tH

3V

1.5V

0V

3V

1.5V

0V

3V

1.5V

0V

3V

1.5V

0V

3095 drw 04

LOW-HIGH-LOW

PULSE

HIGH-LOW-HIGH

PULSE

1.5V

tW

1.5V

3095 srw 05

PROPAGATION DELAY

ENABLE AND DISABLE TIMES

ENABLE

DISABLE

SAME PHASE

INPUT TRANSITION

tPLH

tPHL

3V

1.5V

0V

VOH

CONTROL

INPUT

tPZL

3V

1.5V

0V

tPLZ

OUTPUT

1.5V

OUTPUT

3V

3V

tPLH

tPHL

VOL

NORMALLY SWITCH

LOW

6V

1.5V

0.3V VOL

OPPOSITE PHASE

INPUT TRANSITION

3V

1.5V

0V

OUTPUT

NORMALLY

HIGH

tPZH

SWITCH

GND

tPHZ

1.5V

0V

0.3V VOH

0V

3095 drw 06

NOTES:

3095 drw 07

1. Diagram shown for input Control Enable-LOW and input Control Disable-

HIGH.

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

3. If VCC is below 3V, input voltage swings should be adjusted not to exceed

VCC.

8.14

6

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