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IDT71V256SB12PZ

3.3V CMOS FAST SRAM WITH 2.5V COMPATIBLE INPUTS 256K (32K x 8-BIT)

Integrated Device Technology 

IDT71V256SB

3.3V CMOS STATIC RAM WITH 2.5V COMPATIBLE INPUTS 256K (32K x 8-BIT)

TIMING WAVEFORM OF READ CYCLE NO. 2(1, 2, 4)

t RC

ADDRESS

DATAOUT

tAA

t OH

PREVIOUS DATA VALID

TIMING WAVEFORM OF READ CYCLE NO. 3(1, 3, 4)

CS

DATAOUT

t ACS

tCLZ (5)

NOTES:

1. WE is HIGH for Read cycle.

2. Device is continuously selected, CS is LOW.

3. Address valid prior to or coincident with CS transition LOW.

4. OE is LOW.

5. Transition is measured ±200mV from steady state.

COMMERCIAL TEMPERATURE RANGE

tOH

DATA VALID

3770 drw 07

DATA VALID

t CHZ (5)

3770 drw 08

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)(1, 2, 3, 5, 7)

t WC

ADDRESS

tOHZ (6)

OE

t AW

CS

t AS

tWP (7)

t WR

WE

DATAOUT

DATAIN

t WHZ (6)

(4)

tOW (6)

t DW

t DH

DATA VALID

(4)

3770 drw 09

NOTES:

1. WE or CS must be HIGH during all address transitions.

2. A write occurs during the overlap of a LOW CS and a LOW WE.

3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.

4. During this period, I/O pins are in the output state so that the input signals must not be applied.

5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

6. Transition is measured ±200mV from steady state.

7. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data

to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can

be as short as the spectified tWP.

5

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