IDT71V256SB15PZ Просмотр технического описания (PDF) - Integrated Device Technology
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IDT71V256SB15PZ
Integrated Device Technology
IDT71V256SB15PZ Datasheet PDF : 6 Pages
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IDT71V256SB
3.3V CMOS STATIC RAM WITH 2.5V COMPATIBLE INPUTS 256K (32K x 8-BIT)
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (VCC = 3.3V ± 0.3V, Commercial Temperature Range)
71V256SA12 71V256SA15 71V256SA20
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC
Read Cycle Time
tAA
Address Access Time
12
—
15
—
—
12
—
15
20
—
ns
—
20
ns
tACS
tCLZ(1)
tCHZ(1)
Chip Select Access Time
Chip Select to Output in Low-Z
Chip Select to Output in High-Z
—
12
—
15
5
—
5
—
0
8
0
9
—
20
ns
5
—
ns
0
10
ns
tOE
tOLZ(1)
tOHZ(1)
Output Enable to Output Valid
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
—
6
—
7
3
—
0
—
2
6
0
7
—
8
ns
0
—
ns
0
8
ns
tOH
Output Hold from Address Change
3
—
3
—
3
—
ns
Write Cycle
tWC
Write Cycle Time
tAW
Address Valid to End-of-Write
tCW
Chip Select to End-of-Write
12
—
15
—
9
—
10
—
9
—
10
—
20
—
ns
15
—
ns
15
—
ns
tAS
Address Set-up Time
0
—
0
—
0
—
ns
tWP
Write Pulse Width
9
—
10
—
15
—
ns
tWR
Write Recovery Time
0
—
0
—
0
—
ns
tDW
tDH
tOW(1)
tWHZ(1)
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End-of-Write
Write Enable to Output in High-Z
6
—
7
—
0
—
0
—
4
—
4
—
1
8
1
9
8
—
ns
0
—
ns
4
—
ns
1
10
ns
NOTE:
1. This parameter guaranteed with the AC test load (Figure 2) by device characterization, but is not production tested.
3770 tbl 10
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
t RC
ADDRESS
tAA
OE
CS
DATAOUT
tOE
t OLZ (2)
tACS
t CLZ (2)
NOTES:
1. WE is HIGH for Read cycle.
2. Transition is measured ±200mV from steady state.
tOH
t OHZ (2)
t CHZ (2)
DATA VALID
3770 drw 06
4
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