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IDT74FCT163244APV

3.3V CMOS 16-BIT BUFFER/LINE DRIVER

Integrated Device Technology 

IDT74FCT163244/A/C

3.3V 16-BIT BUFFER/LINE DRIVER

COMMERCIAL TEMPERATURE RANGES

POWER SUPPLY CHARACTERISTICS

Symbol

∆ICC

Parameter

Quiescent Power Supply Current

TTL Inputs HIGH

Test Conditions(1)

VCC = Max.

VIN = VCC – 0.6V(3)

Min. Typ.(2) Max. Unit

— 2.0 30 µA

ICCD

Dynamic Power Supply

Current(4)

VCC = Max.

Outputs Open

50% Duty Cycle

xOE = GND

One Input Toggling

VIN = VCC

VIN = GND

—

50

75 µA/

MHz

IC

Total Power Supply Current(6)

VCC = Max.

VIN = VCC

— 0.5 0.8 mA

Outputs Open

fi = 10MHz

VIN = GND

50% Duty Cycle

xOE = GND

One Bit Toggling

VCC = Max.

Outputs Open

fi = 2.5MHz

50% Duty Cycle

xOE = GND

Sixteen Bits Toggling

VIN = VCC –0.6V

VIN = GND

VIN = VCC

VIN = GND

VIN = VCC –0.6V

VIN = GND

— 0.5 0.8

—

2.0 3.0(5)

—

2.0 3.3(5)

NOTES:

1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.

2. Typical values are at VCC = 3.3V, +25°C ambient.

3. Per TTL driven input; all other inputs at VCC or GND.

4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.

5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.

6. IC = IQUIESCENT + IINPUTS + IDYNAMIC

IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi)

ICC = Quiescent Current (ICCL, ICCH and ICCZ)

∆ICC = Power Supply Current for a TTL High Input

DH = Duty Cycle for TTL Inputs High

NT = Number of TTL Inputs at DH

ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)

fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)

NCP = Number of Clock Inputs at fCP

fi = Input Frequency

Ni = Number of Inputs at fi

2532 tbl 06

SWITCHING CHARACTERISTICS OVER OPERATING RANGE(4)

FCT163244

FCT163244A

FCT163244C

Symbol

Parameter

Condition(1)

Min.(2)

Max.

Min.(2)

Max.

Min.(2)

Max. Unit

tPLH Propagation Delay

tPHL xAx to xYx

CL = 50pF

1.5

6.5

1.5

4.8

1.5

4.1

ns

RL = 500Ω

tPZH Output Enable Time

tPZL

1.5

8.0

1.5

6.2

1.5

5.8

ns

tPHZ Output Disable Time

tPLZ

1.5

7.0

1.5

5.6

1.5

5.2

ns

tSK(o) Output Skew(3)

—

0.5

—

0.5

—

0.5

ns

NOTES:

2532 tbl 07

1. See test circuit and waveforms.

2. Minimum limits are guaranteed but not tested on Propagation Delays.

3. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.

4. Propagation Delays and Enable/Disable times are with VCC = 3.3V ±0.3V, Normal Range. For VCC = 2.7V to 3.6V, Extended Range, all Propagation Delays

and Enable/Disable times should be degraded by 20%.

8.1

4

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