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IDT74FCT163244CPF8
(Rev.:2002)

3.3V CMOS 16-BIT BUFFER/LINE DRIVER

Integrated Device Technology 

IDT74FCT163244A/C

3.3V CMOS 16-BIT BUFFER/LINE DRIVER

INDUSTRIAL TEMPERATURE RANGE

TEST CIRCUITS AND WAVEFORMS

SWITCH POSITION

V CC

VIN

Pulse

Generator

D.U.T

.

RT

500

VOU

Ω

T

50pF

500

CL

Ω

6v

Open

GND

Test

Open Drain

Disable Low

Enable Low

Disable High

Enable High

All Other Tests

Switch

6V

GND

Open

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

Test Circuits for All Outputs

DATA

INPUT

tSU

TIMING

INPUT

ASYNCHRONOUS CONTROL

PRESET

CLEAR

ETC.

SYNCHRONOUS CONTROL

PRESET

CLEAR

CLOCK ENABLE

tSU

ETC.

tH

tREM

tH

Set-up, Hold, and Release Times

SAME PHASE

INPUT TRANSITION

tPLH

tPHL

OUTPUT

tPLH

tPHL

OPPOSITE PHASE

INPUT TRANSITION

Propagation Delay

3V

1.5V

0V

3V

1.5V

0V

3V

1.5V

0V

3V

1.5V

0V

LOW-HIGH-LOW

PULSE

tW

HIGH-LOW-HIGH

PULSE

Pulse Width

1.5V

1.5V

3V

1.5V

0V

VOH

1.5V

VOL

3V

1.5V

0V

CONTROL

INPUT

OUTPUT

NORMALLY

LOW

OUTPUT

NORMALLY

HIGH

ENABLE

DISABLE

tPZ

L

SWITCH

6V

tPZH

tPL

3V

Z

1.5V

tPHZ

SWITCH

GND

1.5V

0V

Enable and Disable Times

0.3V

0.3V

3V

1.5V

0V

3V

VOL

VOH

0V

NOTES:

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

3. if VCC is below 3V, input voltage swings should be adjusted not to exceed VCC.

5

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